One of the most common challenges that board- and system-level engineers face in designing an amplifier driver for a precision successive approximation register (SAR) is optimizing the effective number of bits (ENOB) to achieve lowest power dissipation. In this article we examine the relationships among ENOB, distortion, and noise, as well as the key tradeoffs in achieving the lowest power and best ENOB using three different SAR driver topologies.
Since most modern SAR converters linearly scale analog power dissipation with sampling rate, the drive amplifier quickly can become the dominant source of power when optimizing an application for ENOB. Figure 1 shows a fast Fourier transform (FFT) with the fundamental input signal (VINPUT_RMS ) and the other performance figures of merit (SNR, SINAD, THD) that are key to calculating overall system ENOB.
Table 1 shows how each performance figure of merit is calculated based on amplifier noise (en_AMP_RMS ), analog-to-digital converter (ADC) noise (en_ADC_RMS ), and harmonics in the FFT (en_HARM_RMSx ). Also, to calculate power dissipation, the quiescent current (IQ ), dynamic output current (ΔIOUT ), and analog supply (VS ) are used:
For a larger image of this Table, click here.
Note that the calculation for ENOB uses the SINAD term because it takes into account distortion introduced by passing an AC signal through the drive amplifier, as shown in equation 1:
Figure 2 shows the quantitative relationship among THD, noise, and ENOB for a 16-bit data acquisition system.
Design topologies for the input drive amplifier
Figure 3 shows a fully differential amplifier-I/O driver (FDA), which is very common in applications where distortion is a primary optimization target. Distortion effects can be introduced when there is a large signal change on the inputs that result in AC CMRR errors. These errors show up in the FFT as harmonics that degrade the THD. This driver topology does not suffer from this effect because the inputs are driven in the inverting configuration and the common-mode remains at fixed voltage, typically midscale.
There are two potential shortcomings to the FDA topology shown in Figure 3.
- Noise and settling at higher input bandwidths: The feedback resistors inherently add thermal noise (for example, en =[4kRTBW]0.5 ) which can be filtered (fc =1/[2πRf Cf ]) at the expense of settling time. Balancing the design between noise filtering and recharging CF can become a challenge.
- Power dissipation:
- a. Lower broadband and flicker noise comes at the cost of power.
b. Lowering the values of the feedback resistors (all shown with the same value R) increases the current driven by the output.
c. The ratio of R in the feedback network may need gain for stability, which means the inherent noise will be gained up to the output.
Alternatively, Figure 4 shows a driver configuration that can be easily optimized for low noise and/or power because there are no feedback resistors to contribute thermal noise. This is especially useful in applications where a sensor output is differential and does not require the common-mode level-shift offered by the topology in Figure 3.
Figure 5 shows a “best of both worlds” topology because it separates the common-mode level-shift by the FDA from the function of driving the ADC. This is important because the values of R can be made much larger to reduce power consumption. Additionally, fC1 can be dramatically reduced to filter the added thermal noise, leaving the buffer amplifier to do the job of recharging CF in between ADC conversions.
Ultimately, to minimize distortion effects and therefore maximize ENOB, the following two rules-of-thumb criteria must be observed:
To summarize, SNR, THD, and SINAD are all important parameters that need to be considered together in one figure of merit (ENOB) so that the power required to achieve a desired performance target is not ignored and the appropriate driver topology may be properly selected.
Join us next time when we will cover a basic overview of OFDM and PAPR for non-RF engineers.
- Agarwal, Vinay, 18-Bit, 1-MSPS Data Acquisition (DAQ) Block Optimized for Lowest Power, TI Precision Design (SLAU513), Texas Instruments, July 2013
- Kumar, Vaibav, 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise, TI Precision Design (SLAU515), Texas Instruments, June 2013
- Kumbasi, Amit, 18-bit Data Acquisition System (DAQ) Optimized for Ultra Low Power <1mW, TI Precision Design (SLAU514), Texas Instruments, June 2013
About the author
Matthew Hann, SAR ADC Product Line Manager in the Precision Analog business unit at TI, has 15 years of product expertise, which includes development and applications support in operational amplifiers, 4-20mA transmitters, temperature sensors, difference amplifiers, instrumentation amplifiers, programmable gain amplifiers, and power amplifiers. Through his past role as an applications engineer, Matt developed a focused expertise on the design of analog front-ends for medical applications such as ECG, EEG, EMG, blood glucose monitoring, and pulse oximetry. He received his BSEE from the University of Arizona, Tucson. He can be reached at .
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