Crosstalk can be a significant concern for a clocking device with multiple outputs generating different frequencies. The dominant behaviors of crosstalk can be understood by studying the interaction between the clock being observed (observe clock) and the clock generating the crosstalk (interference clock).
Crosstalk usually manifests itself as spurs on the observe clock as a result of the interference clock. Typically there are two types of crosstalk spurs: direct coupling spurs and intermodulation spurs. The direct coupling spur is at the interference clock frequency (or its harmonics), while the intermodulation spur is at the greatest common divisor (GCD) of the observe and interference frequencies. For instance, if the observe clock is 400MHz and the interference clock is 300MHz, you would expect the direct coupling spur to be at frequencies that are multiples of 300MHz and the intermodulation spur to be at multiples of at GCD[400,300] = 100MHz.
Crosstalk spur mechanisms and mitigations
Crosstalk spurs can be influenced by many factors such as the phase relationship, spur frequency, output location, output format, and power supply decoupling.
Phase relationship can affect the spurs because signals can add constructively or destructively to make the spurs better or worse. Although it is possible to tinker with on-chip output delays to affect spurs, it may not be very repeatable.
The spur frequency is another factor as crosstalk typically increases by 20dB/decade with the spur frequency within some range. See Figure 1.
The choice of which two outputs has a profound impact on the crosstalk and can be used to reduce crosstalk spurs. The general principle of frequency planning is to not use or place the same frequency on outputs with the strongest interaction. For example, the relative crosstalk matrix shown below in Table 1 using the LMK04800 implies that one might want to place the same clock frequencies on output clocks 6 and 8, and perhaps use clock 0 for a different frequency.
The output format of both the observe and interference clocks has an impact on the crosstalk. Reducing the interference clock amplitude and using differential outputs is effective. For CMOS, using opposing polarity, even if only one output is needed, can improve crosstalk. For instance, Table 2 shows that if we change the interference clock format from LVPECL (1600mV, p-p) to LVDS, we can improve the crosstalk spur on the order of 16dB.
Power supply bypassing also can have an impact on crosstalk, especially the intermodulation spur. Many times it is beneficial to isolate supply pins for clocks of different frequencies with series ferrite beads. Bypass capacitors straight to ground, while intuitively the best approach, can often make crosstalk worse because they allow spur energy to couple to the ground plane, and through other bypass capacitors to other output power supply pins.
Sometimes, the ground plane is not as low impedance as you think. If the ferrite bead used is on the other side of the board, ensure the via to this has good clearance from the ground and power plans to prevent unwanted coupling.
Join us next month when we will discuss the move to JESD204B for high-speed data converter digital interfaces: benefits, challenges, and status.
For more information about clocks and timers, visit: www.ti.com/clocksandtimers-ca.
— Dean Banerjee is an applications engineer for TI's Signal and Data Path Solutions Business Unit. He has been involved with phase-locked loop (PLL) frequency synthesizers for over 15 years, and authored a book, “PLL Performance, Simulation, and Design.” He holds a master's degree in applied mathematics from the University of Illinois, and an MSEE degree from Southern Illinois University. Dean can be reached at .
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