Signal Chain Basics #82: Crosstalk Between Outputs in Clocking Devices

Crosstalk can be a significant concern for a clocking device with multiple outputs generating different frequencies. The dominant behaviors of crosstalk can be understood by studying the interaction between the clock being observed (observe clock) and the clock generating the crosstalk (interference clock).

Crosstalk usually manifests itself as spurs on the observe clock as a result of the interference clock. Typically there are two types of crosstalk spurs: direct coupling spurs and intermodulation spurs. The direct coupling spur is at the interference clock frequency (or its harmonics), while the intermodulation spur is at the greatest common divisor (GCD) of the observe and interference frequencies. For instance, if the observe clock is 400MHz and the interference clock is 300MHz, you would expect the direct coupling spur to be at frequencies that are multiples of 300MHz and the intermodulation spur to be at multiples of at GCD[400,300] = 100MHz.

Crosstalk spur mechanisms and mitigations
Crosstalk spurs can be influenced by many factors such as the phase relationship, spur frequency, output location, output format, and power supply decoupling.

Phase relationship can affect the spurs because signals can add constructively or destructively to make the spurs better or worse. Although it is possible to tinker with on-chip output delays to affect spurs, it may not be very repeatable.

The spur frequency is another factor as crosstalk typically increases by 20dB/decade with the spur frequency within some range. See Figure 1.

Figure 1

Simple example of coupling.

Simple example of coupling.

The choice of which two outputs has a profound impact on the crosstalk and can be used to reduce crosstalk spurs. The general principle of frequency planning is to not use or place the same frequency on outputs with the strongest interaction. For example, the relative crosstalk matrix shown below in Table 1 using the LMK04800 implies that one might want to place the same clock frequencies on output clocks 6 and 8, and perhaps use clock 0 for a different frequency.

Table 1

Relative crosstalk matrix based on the LMK04800.

Relative crosstalk matrix based on the LMK04800.

The output format of both the observe and interference clocks has an impact on the crosstalk. Reducing the interference clock amplitude and using differential outputs is effective. For CMOS, using opposing polarity, even if only one output is needed, can improve crosstalk. For instance, Table 2 shows that if we change the interference clock format from LVPECL (1600mV, p-p) to LVDS, we can improve the crosstalk spur on the order of 16dB.

Table 2

Relative crosstalk by output format for the LMK04800.

Relative crosstalk by output format for the LMK04800.

Power supply bypassing also can have an impact on crosstalk, especially the intermodulation spur. Many times it is beneficial to isolate supply pins for clocks of different frequencies with series ferrite beads. Bypass capacitors straight to ground, while intuitively the best approach, can often make crosstalk worse because they allow spur energy to couple to the ground plane, and through other bypass capacitors to other output power supply pins.

Figure 2

Possible supply bypassing recommendation.

Possible supply bypassing recommendation.

Sometimes, the ground plane is not as low impedance as you think. If the ferrite bead used is on the other side of the board, ensure the via to this has good clearance from the ground and power plans to prevent unwanted coupling.

Join us next month when we will discuss the move to JESD204B for high-speed data converter digital interfaces: benefits, challenges, and status.


For more information about clocks and timers, visit:

— Dean Banerjee is an applications engineer for TI's Signal and Data Path Solutions Business Unit. He has been involved with phase-locked loop (PLL) frequency synthesizers for over 15 years, and authored a book, “PLL Performance, Simulation, and Design.” He holds a master's degree in applied mathematics from the University of Illinois, and an MSEE degree from Southern Illinois University. Dean can be reached at .

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13 comments on “Signal Chain Basics #82: Crosstalk Between Outputs in Clocking Devices

  1. Davidled
    October 5, 2013

    High-speed serial data network transmission improvement would be made as studying differential via holes impedance characterization in the PCB. There are a few researches on university and Institute as extracting it to circuit modeling which changes hole size.  I guess that crosstalk would be minimized by this type approach.

  2. goafrit2
    October 10, 2013

    >>  I guess that crosstalk would be minimized by this type approach.

    The best way of designing systems to eliminate cross-talk is making them event-driven and quasi-delay insensitive. In that case, delay or coupling has no effect on effective performance of system because it is asyncrhonous

  3. Netcrawl
    October 10, 2013

    Improvement in PCB layout and design is very important, with good PCB layout and some design rules, crosstalk can be minimized. A good PCB layout design starts with circuit design. Keep on mind the location of each functional blocks, this is very important.

  4. ptessmer
    October 12, 2013

    Dear All, I read the contributions to the Signal Chain Basics series from the very first article. It is going to be 100, soon.  Many students and colegues of mine keep collection of hard copies of the articles. Why not to make a kind of a .pdf file out the existing contributions and make easy integration of future features  ? A kind of living book would result.  Downloading and eventual printing of a “private” copy of it would be less cumbersome as it is today. I hope it is doable.


  5. Davidled
    October 13, 2013

    It sounds like “event-driven” or “quasi-delay insensitive” approaches to CMOS and Chip level.

    I think that cross talk is never-end topics like jitter analysis.  PicoScope 9300 scope is one of tools, providing eye-diagram with crosstalk. Based on engineering experiment, signal line location & via size and location would be reviewed to improve the signal integrity (SI).

  6. goafrit2
    October 14, 2013

    >> A good PCB layout design starts with circuit design

    Yet over the years, I have noticed that the most important factor may the quality of the material that the final PCB is made. Have a great design, use lousy material, you have no chance.

  7. goafrit2
    October 14, 2013

    >> Why not to make a kind of a .pdf file out the existing contributions and make easy integration of future features

    You can copy the files and go to and easily get a PDF in seconds. It is going to be hard to change this as this seems to be the adopted model for all UBM sites.

  8. goafrit2
    October 14, 2013

    >> It sounds like “event-driven” or “quasi-delay insensitive” approaches to CMOS and Chip level.

    The point is that if your design is using asynchronous methodology, cross talk is practically immaterial as the signal degradation will have limited impact.

  9. yalanand
    October 27, 2013

    To raise the value of the conversion from analog to digital, we need to describe a few terms exclusive to the digital zone. These concepts form the substance of the analog-to-digital convert and are self-determining of the technique usage to digitize the indicator. 

  10. Dean Banerjee
    October 28, 2013

    Thank you for your feedback.   With vias, the problem that I have seen is that there is a tendency to put the ground and power planes too close to them and this is a great way for noise energy to couple.  Now this is talking about vias that go to the ground and power planes, so I don't know how critical impedance of this is, because it's DC.  But for other higher frequency signals, like clock outputs, then the via inductance is definitely a much bigger consideration.

  11. Dean Banerjee
    October 28, 2013

    I agree with this and seen it on many on the EVM boards I have created for TI where power supply of one block injects noise on another block.   This phenomenon can manifest itself as crosstalk in clocking devices, fractional spurs, or crosstalk between two VCOs on a dual PLL synthesizer.  At some point, the layout does become important, but before that, if the power supplies for the critical blocks producing different frequencies are not isolated, then this is an invitation for spurs to mix and match.

  12. Netcrawl
    October 28, 2013

    A complete ground is important and essential,  the best solkutions is to have its own layer and ground planes for every voltage, we need to take a first look at this one.

    I think it depends on ESr(equivalent series resistance) and ESL(equivalent series inductance , a good combination of capacitors could lead to a low impedance.

  13. Dean Banerjee
    October 29, 2013

    Good Discussion…

    Indeed, a complete ground is essential for good performance.  From personal experience, I did a board one time where I broke it up and attempted to minimize spurs and I got very erratic and unpredictable spurs that were sensitive to things like touching the part with my finger.

    That being said, power supply pins can also generate soyrs that can be transferred to the ground plane and that can show up on other outputs.  For your idea o making plane for each supply voltage, then if two supply pins to different clock outputs have the same voltage, but different frequencies, then they will inject spurs onto each other.

    If capacitors are placed between the power pin and ground, then the intention is to have a low impedance and kill any noise.  But often seems that instead of killing the noise, it more like redirects it and this spur energy gets on the ground plane.

    On the LMK04828 evaluation board, (, on page 34, we actually put an inductor on the power supply of the VCXO because we found it was injecting noise to the ground plane.  For this board, we also put a 0 ohm resistor and we went back and forth on which one was better for this spur.

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