Signal Chain Basics #83: JESD204B for High-Speed Data Converter Digital Interfaces

As sample rates for high-speed data converters have increased by a factor of 10 over the last decade, a more efficient digital interface is needed to keep pace. In the coming years, the digital interface for most high-speed data converters will change from parallel LVDS to a clock-embedded, multi-lane serial link standard called JESD204B . The implications of this change are huge. This article discusses the JESD204B standard, benefits, and challenges for data converter users.

The biggest benefits are a reduction in interface lines and an easing of layout tolerances. For example, the DAC34SH84 with parallel LVDS interface is one of the widest bandwidth interpolating digital-to-analog converters (DACs) available today. To support four 16-bit channels, 32 LVDS lanes support four channels at 750MSPS per channel. With a bit rate of 1.5 Gbit/s, the LVDS lines should be matched in length to less than 1 cm (< 60 ps on FR4 PCB).

Table 1 compares a JESD204B versus LVDS interface. JESD204B supports lanes running up to 12.5 Gbit/s that, after 8-bit/10-bit formatting, results in up to 625MSPS per lane, or 6.6 times higher than the LVDS interface. Although the bit rate is high, since the clock is recovered from the serializer/deserializer (SerDes) lane and the data from each lane are realigned in the receiver, the routing matching between lanes is no longer critical.

Table 1

Comparison of parallel LVDS with JESD204B DAC

Comparison of parallel LVDS with JESD204B DAC

Figure 1 compares the DAC34SH84 LVDS interface layout (a) to a JESD204B interface DAC (b). The LVDS interface length matching requires squiggles to lengthen the shorter traces, increasing the total interface PCB area, and it also uses three PCB layers. By contrast, the JESD204B lanes do not need to be matched in length and can be routed on the top PCB layer only.

Figure 1a

Figure 1b

LVDS (a) and JESD204B (b) DAC layouts compared

LVDS (a) and JESD204B (b) DAC layouts compared

The move to a SerDes interface has had challenges such as power dissipation of the interface. Figure 2 shows the power efficiency (sample rate in MSPS per mW of power dissipation) of the interface and pin efficiency (MSPS per pin) versus interface technology. The plot combines the DAC receiver and ADC transmitter power. In the early 2000s, most high-speed data converters utilized a power-efficient CMOS interface. In the mid-2000s, parallel LVDS interfaces were introduced.

Figure 2

Pin and power efficiency of data converter interface technology

Pin and power efficiency of data converter interface technology

The first JESD204A devices in 2010 were limited to a bit rate of 3.125 Gbit/s — only twice as pin efficient as the highest LVDS interfaces. Most of these devices were in older process technologies with power inefficient SerDes circuits, reducing power efficiency by 20 times.

In 2012, the first JESD204B devices still had high-power SerDes but were unable to utilize the full speed of the JESD204B interface standard. By 2014, data converters in advanced processes compatible with high-speed, power-efficient SerDes interfaces will be available, eliminating the power penalty of JESD204B over LVDS interface.

JESD204B solves multi-chip synchronization with the introduction of subclass 1, which utilizes a synchronization signal (SYSREF) to provide a deterministic latency across the interface.

There are two areas where JESD204B may be disadvantageous over LVDS interface. First, additional encoding/decoding circuits add latency to the interface. Comparing the ADS42JB69 (16-bit, dual 250MSPS ADC) with JESD204B interface to the similar ADS42LB69 with parallel LVDS interface, the JESD204B interface has nine clock cycles of additional latency. Another drawback is that a constant clock frequency is required to prevent the interface from losing lock.

The majority of systems utilizing high-speed data converters should be able to take advantage of upcoming JESD204B data converters to simplify board design.

Join us next month when we discuss why RS-485 does not need ground wires.

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About the author
Robert Keller is the Systems Manager for High-Speed Data Converters. He has 10 years of experience supporting high-speed products in wireless infrastructure communication, test and measurement, and military systems. He received a BA in physics and mathematics from Washington University, St. Louis, and a PhD in applied physics from Stanford University. He has 10 US patents in networking and sensor applications. He can be reached at .

2 comments on “Signal Chain Basics #83: JESD204B for High-Speed Data Converter Digital Interfaces

  1. Davidled
    November 5, 2013

    I thought that wireless communication would get a huge benefit from high speed Data Converter. I wonder if there is any heating or temperature comparison between LVDC and JESD204B DAC during the execution time period in the same board design.  I guess that JESD204B get more heating than DAC 34SH84 because it has 12.5 Gbps and also table shows in the 2014.

  2. samicksha
    November 6, 2013

    You are right Daej, JESD204B lane rate up to 10 Gbps, optimized for high-speed signal such as 3G/4G, understanding lane rate is important here, the selection of the right JESD204B converter can be simplified by focusing on just a few high-level criteria to mate with its FPGA.

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