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Signal Chain Basics #89: Creating Clock Trees From Multiple Devices, Part 1

This two-part Signal Chain Basics post is brought to you by Dean Banerjee, an applications engineer for TI's Signal and Data Path Solutions Business Unit.

Introduction
Clock trees are a collection of one or more devices used to create multiple clock output frequencies and formats. In many cases, a single device can generate all the required outputs and is the best solution. However, there are other cases where a single device may not be the most optimal, or even possible. This article discusses some of the considerations of multiple versus single-device solutions.

Synchronization of multiple divided outputs
When a frequency is divided by a set of unsynchronized dividers (Figure 1), the divided outputs have an ambiguous phase relationship. In this case, there are four possible phases, and these outputs could be off by 0, ¼, ½, or ¾ cycle.

Figure 1

Three-device solution with asynchronous output phases.

Three-device solution with asynchronous output phases.

Sometimes frequencies can be arranged to avoid this issue. Other cases require a synchronization pulse that is sent away from the rising edges of the input clock. This pulse can be produced by a SYSREF output of a JESD204B clocking device, or the complimentary side of an output clock.

Cascading of phase noise
When one device drives another, the phase noise cascades from one to the next, depending on what the devices are and how they are hooked together. If buffers are used to drive buffers, their noise floors will add together. For this reason, often a good approach is to use buffers in a parallel configuration instead of in series. Another common situation is when a buffer is added to get more outputs from a clock generator. Typically, adding a buffer degrades the noise floor noticeably and the jitter only slightly (Figure 2).

Figure 2

LMX2531LQ1226E + LMK00301 solution. Following are simulations of the single and combined devices (Figures 2a and 2b).

LMX2531LQ1226E + LMK00301 solution. Following are simulations of the single and combined devices (Figures 2a and 2b).

Figure 2a

One device: jitter = 358.5 fs; noise floor = -157.8 dBc/Hz.

One device: jitter = 358.5 fs; noise floor = –157.8 dBc/Hz.

Figure 2b

Both devices: jitter = 359.9 fs; noise floor = -152.5 dBc/Hz.

Both devices: jitter = 359.9 fs; noise floor = –152.5 dBc/Hz.

Part two (Signal Chain Basics #89: Creating Clock Trees From Multiple Devices, Part 2) will discuss current consumption, jitter, and cost, as well as crosstalk and routing.

2 comments on “Signal Chain Basics #89: Creating Clock Trees From Multiple Devices, Part 1

  1. dyanjoy
    May 14, 2014

    The signal Chain basics #89 let us know about the Clock Trees from multiple devices. I am really enjoying reading your well written articles. I think you spend numerous effort and time updating your blog. I have bookmarked it and I am taking a look ahead to reading new articles. Please keep up the good articles! 

  2. etnapowers
    May 16, 2014

    The three-device solution with asynchronous output phases is a good solution to generate two clock signals at the same frequency. In this IC the matching between the clock lines is very important to avoid a drift of the output frequency and the cross talking between clock signals.

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