This two-part Signal Chain Basics post is brought to you by Dean Banerjee, an applications engineer for TI's Signal and Data Path Solutions Business Unit.
Clock trees are a collection of one or more devices used to create multiple clock output frequencies and formats. In many cases, a single device can generate all the required outputs and is the best solution. However, there are other cases where a single device may not be the most optimal, or even possible. This article discusses some of the considerations of multiple versus single-device solutions.
Synchronization of multiple divided outputs
When a frequency is divided by a set of unsynchronized dividers (Figure 1), the divided outputs have an ambiguous phase relationship. In this case, there are four possible phases, and these outputs could be off by 0, ¼, ½, or ¾ cycle.
Sometimes frequencies can be arranged to avoid this issue. Other cases require a synchronization pulse that is sent away from the rising edges of the input clock. This pulse can be produced by a SYSREF output of a JESD204B clocking device, or the complimentary side of an output clock.
Cascading of phase noise
When one device drives another, the phase noise cascades from one to the next, depending on what the devices are and how they are hooked together. If buffers are used to drive buffers, their noise floors will add together. For this reason, often a good approach is to use buffers in a parallel configuration instead of in series. Another common situation is when a buffer is added to get more outputs from a clock generator. Typically, adding a buffer degrades the noise floor noticeably and the jitter only slightly (Figure 2).
Part two (Signal Chain Basics #89: Creating Clock Trees From Multiple Devices, Part 2) will discuss current consumption, jitter, and cost, as well as crosstalk and routing.