The electrostatic discharge (ESD) ratings in component data sheets often confuse system designers by not specifying the actual standard to which a component was tested. The following explains the differences between the two most commonly applied ESD standards, the human body model (HBM) and the IEC 61000-4-2 standard.
There are two categories of ESD: component-level ESD and system-level ESD. Component-level ESD is necessary in the manufacturing environment where component assembly, packaging, and shipping can cause ESD damage to a single device. Here the HBM standard is applied, simulating a charged person’s discharge through the device under test (DUT) to ground.
Because component assembly, packaging, and shipping are performed in a controlled ESD environment through the application of ESD protective gear, the ESD stress upon a component is drastically reduced. Hence, the HBM test presents a rather soft ESD test. This is sufficient for controlled environments, but inadequate for systems in uncontrolled ESD environments.
System-level ESD is required in the uncontrolled end-user environment where, for example, a charged user can subject a handheld device to ESD levels of up to 40 kV by touching connector pins when plugging or unplugging cables.
To better rate a system’s ESD vulnerability, the IEC 61000-4-2 standard was developed. It replicates a charged person discharging via a metal object, such as a screw driver, into a grounded electrical system.
Differences between HBM and IEC 61000-4-2
The main differences between the HBM and the IEC 61000-4-2 standards are the number of strikes applied during testing and the generator models (Figure 1), which create differences in the waveforms’ rise times and peak currents (Figure 2).
The pulse rise times of the two waveforms differ largely. The rise time of an HBM strike can extend up to 25 ns when discharging into a 500 ohm resistor, while the rise time of an IEC 61000-4-2 strike is less than 1 ns. Hence an ESD structure designed for an HBM strike might not turn on when exposed to IEC-ESD strikes, and the circuit to be protected becomes damaged.
The amount of peak current is critical to whether or not a component survives an ESD strike. It is possible for an IC to survive an 8 kV HBM strike but fail at a much lower, 2 kV IEC-ESD strike.
The number of ESD strikes in the HBM specification is limited to a single positive and a single negative strike, whereas IEC 61000-4-2 requires a minimum of 10 positive and 10 negative strikes. Therefore, during an HBM test it is possible to survive the first strike, but fail on subsequent strikes due to damage sustained in the first strike.
For equal test voltages the energy content of an IEC-ESD pulse is 7.56 times higher than that of an HBM-ESD pulse, and for equal energy content, the ratio of an HBM to an IEC ESD test voltage is:
Equation 2 allows determining the maximum HBM test voltage for an ESD protection circuit passing a maximum IEC-ESD strike. For example, a protection structure successfully passing a sequence of 16 kV IEC ESD strikes is able to withstand a single HBM strike of:
However, the opposite, that a 44 kV HBM ESD structure can withstand a 16 kV IEC strike, is not likely as it won’t switch fast enough to catch the short front time of an IEC ESD pulse.
Because end-user applications are subjected to many ESD strikes during their lifetimes, system designers must be aware of misleading ESD specifications in component data sheets.
Devices complying with the IEC 61000-4-2 standard usually indicate this fact, while those that don’t are commonly tested to the HBM standard.
— Thomas Kugelstadt