The phase-locked loop (PLL) in Figure 1 works by starting with a stable input frequency (fOSC ). It is divided down by R to get the phase detector frequency (fPD ), then multiplied by N to get the voltage-controller oscillator (VCO) frequency (fVCO ). Finally, it is divided down by D to get the output frequency (fOUT ). The output divider, D, is typically an integer, but it is possible for the N divider to be fractional. Devices can exist with multipliers on the input path, effectively making R fractional.
Integer boundary spurs and generation of unrelated frequencies
In cases where fOUT is not nicely related to fOSC , this can cause the N divider to be a fractional value (Figure 2 ). This produces fractional spurs that can substantially degrade jitter. Typically, spurs are most severe when the N divider value is slightly off from an integer value. In particular, the integer boundary spur occurs at an offset equal to the distance of the N divider value to the closest integer value multiplied by the phase detector frequency. In this case: 0.0024 x 100 MHz = 240 kHz.
Mitigating spurs by changing the VCO frequency
One way to mitigate spurs is to shift the VCO frequency to a different value, if the output divider and VCO can accommodate this as shown in Figure 3 . Here the integer boundary spur is moved from 200 kHz to 50.21 MHz, which is much easier to filter.
Mitigating spurs by changing the phase detector frequency
In situations where the VCO does not have enough tuning range to stay away from the integer boundary frequencies, a multiplier in the input path can be used. For example, the LMX2572 has a similar structure to Figure 1 with the addition of a multiplier in the input path and a fixed divide by two in the feedback path. To illustrate how the multiplier can be used to avoid integer boundaries, consider producing a frequency of 1024 MHz from a 20 MHz XO (Figure 4 ).
Now consider what can be done if the input frequency is 19.99985 MHz, which leads to an output frequency of 1023.9927 MHz. In order to correct for this frequency error, you could program a new target output frequency:
The new target frequency is higher than expected, if the input frequency is 20 MHz. However, because it is smaller, this corrects out the issue (Figure 5 ).
Although the frequency error has been corrected with the fractional value, this generates an integer boundary spur at an offset of 19.99985 MHz * 0.00096625 = 19.3 kHz (Figure 6 ).
When the multiply of four and divide by three are used in the input path (Figure 7 ), the integer boundary spur is shifted away (Figure 8 ). Note that the charge pump gain is adjusted to keep the loop bandwidth constant.
When the multiply of four and divide by three are used in the input path, the spectrum is obtained (Figure 8 ). Note that the charge pump gain is adjusted to keep the loop bandwidth constant.
When the input and output frequencies are not nicely related and cause the N divider to be a fraction, sometimes fractional spurs can be mitigated by shifting the VCO frequency or phase detector frequency as shown in these examples.
Please join us next time when we will discuss data converter noise. Could a 16-bit ADC really be lower noise than a 24-bit ADC?
- Banerjee, Dean. “PLL Performance, Simulation, and Design – Fourth Edition” Dogear Publishing, 2006
- Download the LMX2571 datasheet
About the Author
Dean Banerjee is an applications engineer for TI’s Signal and Data Path Solutions Business Unit. He has been involved with phase-locked loop (PLL) frequency synthesizers for over 17 years. Dean has also authored two books: “PLL Performance, Simulation, and Design,” and “From Continuous to Discrete.” He holds a master’s degree in applied mathematics from the University of Illinois, and an MSEE degree from Southern Illinois University.