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Signal Chain Basics #104: Understanding noise in ADCs

As a data converter supplier, we are sometimes asked, which is our lowest noise analog-to-digital converter (ADC)? While the tendency is to assume an ADC with the highest resolution would be the right answer, this is not necessarily the case. But before answering the question, we will discuss different types of noise found in ADCs.

There are many different sources of noise in an ADC, which can be grouped into three different categories based on their frequency characteristics: 1/f noise, white noise, and phase noise. A common way to characterize an ADC is to use an input tone and perform a Fourier transform of the output. Figure 1 shows a simplified frequency spectrum of an ADC output with the different noise characteristics.

Figure 1

Frequency spectrum of an ADC output showing noise characteristics

Frequency spectrum of an ADC output showing noise characteristics

Noise spectral density (NSD) is the noise power per unit of frequency, often expressed as dB/Hz. For an ADC, the NSD is usually referenced to the power of a full-scale tone, which is written as dBFS/Hz.

White noise, also known as broadband noise, has a flat PSD. Sources of white noise include quantization noise, thermal noise, and MOS transistor channel noise. Quantization noise is due to the error introduced when converting an analog signal into a digital signal with discrete amplitude values – the noise energy comes from the difference between the analog and digital values of the signal. Thermal noise is due to thermal movements of electrons in resistors and capacitors. For ADCs with a track and hold capacitor, the thermal noise of the sampling capacitor often dominates the white noise of the ADC. MOS transistor channel noise is due to thermal noise in the MOS transistor channel.

Note that 1/f noise, also known as flicker noise, is due to populating and depopulating of traps in transistors. The PSD of 1/f noise increases inversely with frequency, and therefore is the dominant noise near DC.

Phase noise is due to errors in the sample time of the ADC, and can be due to both the noise on the input clock and the internal ADC clocking circuits. Phase noise modulates with the input signal, and generally has a low frequency component near the input signal and a broadband component that adds to the ADC white noise.

Figure 2 shows the output noise spectrum for a dual-channel, 16-bit 1 GSPS ADC (ADS54J60) with a 105 MHz input tone (note that the spur level is not accurate in the plot in the interest of highlighting the noise spectrum). Below 5 MHz 1/f noise dominates, and within +/–5 MHz of the input tone phase noise dominates. The white noise is flat with a value of –159 dBFS/Hz.

The signal-to-noise ratio (SNR) specification for ADCs is the sum of all noise sources in the ADC relative to the input signal power. SNR is often expressed as an effective number of bits, where the noise is compared to quantization noise for a theoretical resolution using

SNR(dB)=1.76+6.02×ENOB (1)

For high-speed ADCs, this is usually dominated by white noise, and so dividing the SNR by the Nyquist bandwidth can be a good approximation of the white noise. For example, the ADS54J60 has an SNR of 71 dBFS with a 100 MHz input, resulting in –159 dBFS/Hz NSD, similar to what is shown in Figure 2 . However, for frequencies within 5 MHz of DC or the input signal, this is not accurate due to the 1/f and phase noise.

Figure 2

ADC at 1 GSPS with 105 MHz Input showing 1/f, phase and white noise (note: spur level not accurate)

ADC at 1 GSPS with 105 MHz Input showing 1/f, phase and white noise (note: spur level not accurate)

Returning now to the question of the lowest noise ADC, let us compare two different ADCs: the ADS1672 (24-bit, 625 kSPS) versus the ADS54J60. SNR for the 24-bit ADC is 102 dB at 625 kSPS which translates to a NSD of –158 dBFS/Hz, compared to the NSD of the 16-bit ADC of –159 dBFS/Hz. Although the 16-bit ADC has 31 dB worse total noise, because it is spread out over a much wider bandwidth, NSD is actually lower than the 24-bit ADC. However, for low frequency (< 5 MHz) range where the 24-bit ADC would typically be used, the 1/f noise of the 16-bit ADC dominates the NSD and has a lower NSD.

Please join us next time when we will discuss the importance of input common-mode range for industrial transceivers.

References

Here is more information about data converters.

Download this datasheet: ADS1672.

About the Author

Editor’s note: Robert Keller and I did some really exciting and interesting work in high speed in the past as colleagues. He’s one of the best high speed experts I know

Robert Keller is a Systems Manager in TI’s High-Speed Products group. He has 14 years of experience supporting high-speed products in wireless infrastructure communication, test and measurement and military systems. He received a B.A. in Physics and Mathematics from Washington University, St. Louis, Missouri, and a Ph.D. in Applied Physics from Stanford University. He has 10 US patents in networking and sensor applications. Robert can be reached at ti_robertkeller@list.ti.com.

1 comment on “Signal Chain Basics #104: Understanding noise in ADCs

  1. jonharris0
    August 26, 2015

    I enjoyed the read and I think readers will find this useful.  I think many don't understand the difference in broad band vs close in noise and your post does a good job summarizing.  Perhaps some additional information on the phase noise (jitter) of the input clock source would be nice as well.  I see this quite often where SNR performance of a particular ADC is not being met and the culprit is a poor input clock source.  Overall, nice job here!

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