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SIGNAL CHAIN BASICS (Part 33): Use an op amp to drive a precision ADC

(Editor's note : there is a complete, linked list of previous installments of this series below the About the Author section at the end.)

Most precision analog-to-digital converters (ADCs) do not have a high-impedance input. The input signal connects directly to a sampling capacitor through a switch. This load presents some interesting challenges.

Some people attempt to verify operation of their ADC by connecting a potentiometer directly to the input, as shown in Figure 1 . This usually disappoints, as the results obtained are less than ideal. The signal seen at the ADC input in this case shows large spikes due to the current required to charge the sampling capacitor being drawn through the large input impedance.

If these settle out within the acquisition time, tACQ , of the converter, then these are of no concern. However, if they do not settle to within 0.5 least significant bits (LSBs) within tACQ , accuracy is lost.



Figure 1: High source impedance causes a loss of accuracy

(Click on image to enlarge)

Figure 2 shows the recommended circuitry for driving a precision ADC. CSH is the sampling capacitor inside the ADC, and RSW is the on-resistance of the sampling switch (usually low enough to be ignored). The sampling switch is closed during the acquisition time, tACQ , of the converter.



Figure 2: Recommended circuit to drive precision ADCs

(Click on image to enlarge)

The external CFLT is used to provide the instantaneous current needed to charge CSH , and must be at least 20× CSH . Typically, 1 nF is suitable. RFLT is used to prevent the driving op amp from seeing a purely capacitive load. RFLT and CFLT then create an RC circuit with a time constant of τ = RFLT CFLT .

To assure everything settles in time for an accurate signal acquisition, tACQ must be &#8805kτ, where
k = ln (2 (N+1) );
k is the number of time constants required to settle to 0.5 LSB for an N-bit converter. From this you can determine the maximum value of τ and the value for RFLT .

The critical parameter in selecting the driving op amp is its unity gain bandwidth, which must be
4(1/(2π RFLT CFLT ))
in order to settle fast enough. This requirement often escapes designers who may select a much slower op amp than required, with disappointing results.

For more information on the sampling process, calculation of the RC time constant, and proper op amp selection see:

  1. M. Oljaca and J. McEldowney, “Using a SAR Analog-to-Digital Converter for Current Measurement in Motor Control Applications,” (SBAA081), October 2002.
  2. R. Downs and M. Oljaca, “Designing SAR ADC Drive Circuitry, Part I: A Detailed Look at SAR ADC Operation,” February 2006.
  3. M. Oljaca and B. Mappes, “ADS8342 SAR ADC Inputs,” (SBAA127), January 2005.
  4. R. Downs and M. Oljaca, “Designing SAR ADC Drive Circuitry Part II: Input Behavior of SAR ADCs”, October 2006.
  5. R. Downs and M. Oljaca, “Designing SAR ADC Drive Circuitry Part III: Designing The Optimal Input Drive Circuit For SAR ADCs”, March 2007.
  6. B. Baker and M. Oljaca, “External components improve SAR-ADC accuracy,” EDN , June 7, 2007, pp 67-75.
  7. M. Oljaca and B. Baker, “Start with the right op amp when driving SAR ADCs,” EDN , October 16, 2008, pp 43-54.

Next month, join us as we discuss audio interfaces.

About the Author

Rick Downs is applications engineering manager for Texas Instruments' Precision Analog group, Tucson, Arizona. Over the past 23 years, Rick has held various positions in applications and marketing of analog semiconductors focused on audio, data acquisition, digital temperature sensors and battery management products. Rick received his BSEE from the University of Arizona, and holds four patents. He has authored several articles and application notes on analog topics, and prepared and delivered several seminars on data acquisition. You can send your questions to Rick at scb@list.ti.com.

Previous installments of this series:

  • SIGNAL CHAIN BASICS (Part 32): Digital interfaces (con't) — The I2 C Bus, click here
  • SIGNAL CHAIN BASICS (Part 31): Digital interfaces (con't) — The SPI Bus, click here
  • SIGNAL CHAIN BASICS (Part 30): Protocol selection over IEEE 802.15.4 silicon, click here
  • SIGNAL CHAIN BASICS (Part 29): Digital interfaces – Single-ended versus differential interfaces, click here
  • SIGNAL CHAIN BASICS (Part 28): Building (Electrical) Bridges, click here
  • SIGNAL CHAIN BASICS (Part 27): Control EMI resulting from board-level clock distribution, click here
  • SIGNAL CHAIN BASICS (Part 26): How to close timing on High-Speed ADCs, click here
  • SIGNAL CHAIN BASICS (Part 25): Designing the audio-signal chain for non-audio experts, Part 1, click here
  • SIGNAL CHAIN BASICS (Part 24): Basic networking using the IEEE 802.15.4 PHY/MAC protocol, click here
  • SIGNAL CHAIN BASICS (Part 23): EIA-485: Receiver equalization boosts networking performance, click here
  • SIGNAL CHAIN BASICS (Part 22): Phantom microphone power–the ghost in the machine, click here
  • SIGNAL CHAIN BASICS (Part 21): Understand and configure analog and digital grounds, click here
  • SIGNAL CHAIN BASICS (Part 20): Understand the basics of op amps and speed, click here
  • SIGNAL CHAIN BASICS (Part 19): Exploring and understanding linear voltage regulators, click here
  • SIGNAL CHAIN BASICS (Part 18): The op amp as integrator, click here
  • SIGNAL CHAIN BASICS (Part 17): Hysteresis–Understanding more about the analog voltage comparator, click here
  • SIGNAL CHAIN BASICS (Part 16): Understanding the analog voltage comparator, click here
  • SIGNAL CHAIN BASICS (Part 15): Analog/digital converter–dynamic parameters, click here
  • SIGNAL CHAIN BASICS (Part 14): Analog/digital converter–static parameters, click here
  • SIGNAL CHAIN BASICS (Part 13): Putting the Bode plot to use, click here
  • SIGNAL CHAIN BASICS (Part 12): The Bode plot, an essential ac-parameter display tool, click here
  • SIGNAL CHAIN BASICS (Part 11): Introducing voltage- and power-conditioning circuits, click here
  • SIGNAL CHAIN BASICS (Part 10): Exploring the Delta-Sigma Converter, click here
  • SIGNAL CHAIN BASICS (Part 9): SAR Converter Operation Explored, click here
  • SIGNAL CHAIN BASICS (Part 8): Flash- and Pipeline-Converter Operation Explored, click here
  • SIGNAL CHAIN BASICS (Part 7): Op Amp Performance Specification–Bias Current, click here
  • SIGNAL CHAIN BASICS (Part 6): Op Amp Input Voltage Offset, click here
  • SIGNAL CHAIN BASICS (Part 5): Introduction to the Instrumentation Amplifier, click here
  • SIGNAL CHAIN BASICS (Part 4): Introduction to analog/digital converter (ADC) types, click here
  • SIGNAL CHAIN BASICS (Part 3): Analog and the digital world, click here
  • SIGNAL CHAIN BASICS (Part 2): Op Amp–Basic operations, click here
  • SIGNAL CHAIN BASICS: Operational Amplifier–The Basic Building Block, click here

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