Editor’s Note : Our guest blogger is Robert Keller, Systems Manager for High-Speed Data Converters. He has ten years of experience supporting high-speed products in wireless infrastructure communication, test and measurement and military systems. He received a B.A. in Physics and Mathematics from Washington University, St. Louis, Missouri, and a Ph.D. in Applied Physics from Stanford University. He has 10 US patents in networking and sensor applications. Robert can be reached at firstname.lastname@example.org. I can personally speak for Robert’s expertise in high speed systems from my experiences traveling with him many times to key customers when I was at TI.
High-speed ADC technology above 1 GSPS has increased in sample rate and performance over the last five years, with new devices enabling direct sampling of the RF spectrum. These new analog-to-digital converters (ADCs) are capable of sampling signals with greater than 1 GHz of bandwidth at frequencies of 3 GHz or higher while maintaining excellent noise and linearity. Higher sample rates are the key in enabling this functionality, with faster sample rates enabling large reductions in size and power for wide bandwidth RF digitizers.
Consider, for example the ADC12J4000, a 12-bit 4-GSPS ADC, and how this could be used to sample a 1 GHz bandwidth signal directly at RF. Its input bandwidth of 3.3 GHz allows sampling of the signal in second Nyquist zone. To prevent other signals outside the intended digitized band from interfering with the digitized signal, an anti-alias filter is required to reduce the out-of-band signals in other Nyquist zones from aliasing into the intended signal.
Centering the sampled signal in second Nyquist zone and using a filter with 60 dB rejection at the closest alias frequency of 1.5 GHz, a shape factor of 3:1 is required. In comparison, while theoretically a lower sample rate such as 2.5 GSPS centered in third Nyquist could also be used, the shape factor of the anti-alias filter required would be 1.5:1 (a lower shape factor is more difficult). The easier filter requirement with the higher sample rate enables a large savings in system size, weight, and cost of the filter by reducing the number of resonators or dipoles required.
In many applications such as signal intelligence, electronic countermeasures and satellite communications, a frequency range of 10 GHz or higher in the microwave or higher bands are required to be digitized. This is typically done by down-converting the signal to 2-4 GHz for digitization with a GSPS ADC. Each chain requires separate amplifiers, a mixer, synthesizer, filter and ADC.
The higher the ADC’s sample rate, the fewer signal chains are required. For example, assuming a 70 percent occupied bandwidth, a 2.5 GSPS ADC requires 12 separate down converter stages, while a 4 GSPS ADC only requires seven. This translates directly into a 42 percent reduction in size, power and weight for the digitizer.
Faster sample rates also improve performance, power and density for narrower bandwidth systems. Consider, for example, the scenario shown in Figure 1 . A 100 MHz signal is located in a 1.5 GHz band centered at 3 GHz, sampled by the ADC at 4 GSPS. After sampling, the integrated digital down-converter in the ADC can be used to isolate the wanted signal and filter all unwanted noise and interfering energy outside of the wanted signal.
The sample rate can then be reduced by 32 times to 125 MSPS complex, just enough to support the wanted signal bandwidth. Similar to how more samples improve signal-to-noise ratio (SNR) by the square root of the number of samples, the SNR of the decimated data is higher than the ADC SNR by 10*log10 of the ratio of ADC and output sample rates. With the lower output sample rate, the ADC12J4000’s flexible JESD204B interface could output the signal through just one serializer/deserializer (SERDES) lane, allowing a large number of ADCs to be connected to a single FPGA with a lower interface power per ADC.
For system designers of wideband RF digitizers, faster really is better.
Join us next time when we will discuss the impending move of industrial space to 3.3V CAN transceivers.
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