One useful dynamic application of μCs is as analog-to-digital converters (ADCs). ADCs over the years have gone from complete DVMs as instruments to embedded subsystems, to a few components. This two-part article presents some minimalist techniques for implementing μC-based ADCs.
Minimalist A/D Conversion
Multiple schemes have been devised over the years for A/D conversion. Some are simple, not very fast, and not very precise, such as the single ramp converter , as shown below; charge a capacitor with a current source, thereby generating a ramp.
When the ramp crosses the unknown voltage, vx , to be measured, the time interval from the start of the ramp to vx , as detected by the comparator, is measured. For a (linear) ramp, the time is proportional to vx . A counter is reset (or overflows) at the start of the ramp and counts an accurate clock, such as a prescaled crystal-controlled μC clock. The ramp voltage is reset by a single transistor.
This ADC is easily implemented using a μC, and requires one counter, an input-port bit from the comparator and an output-port bit to reset the ramp. The ramp ADC is subject to inaccuracy because ramp slope variation can be caused by the ramp current source, capacitor drift, and comparator input-voltage offset and bias-current errors. It is conceptually simple, but we can do far better than this with fewer components.
Another category of ADCs are the parallel-feedback types. They use a DAC and comparator to set bits of the converted measurement. The general scheme is shown below.
Depending on the logic, the converter can be one of multiple types. The successive-approximation scheme is predominant because it converts one bit per iteration, which takes n cycles to convert n bits independent of the converted value of vx . This scheme is well-suited for μC-based A/D conversion.
μC-Based Parallel-Feedback ADCs
The parallel-feedback converter can be adapted to most μCs as shown below.
The μC performs the logic. For the simplest and least desirable ADC, the ramp converter, the μC logic is given in algorithmic form below:
0. Ramp ADC
1. Set OUT to zero: OUT ← 0.
2. Input the IN bit.
3. If IN = 0, then VX ← OUT; go to 1.
Else increment OUT: OUT ← OUT + 1.
4. Output OUT; go to 2.
The second ADC option, also differing from the others in its logic, is the tracking ADC . The advantage of the tracking converter is that it follows the analog waveform, though it is subject to digital slew-rate limitations for fast changes in vx . The tracking algorithm is given below.
0. Tracking ADC
1. Output OUT.
2. Input IN.
3. If IN = 0, then decrement OUT: OUT ← OUT – 1.
Else, increment OUT: OUT ← OUT + 1.
4. Set VX to OUT: VX ← OUT.
5. Go to 1.
This algorithm is not more complicated than that of the ramp converter but has the real-time tracking advantage. If the input waveform changes too quickly, the tracking ADC has the disadvantage that its DAC output slews, taking multiple iterations to “catch up” with the waveform and once again track it accurately.
The successive-approximation (SA) ADC uses the SA algorithm which is somewhat more involved but has the advantage of constant, input-independent conversion time. It uses two memory locations labeled SAR and SR. C is the processor carry bit.
0. Successive-Approximation ADC
1. Clear SR and SAR: SR ← 0; SAR ← 0.
Set C to one: C ← 1.
2. Rotate SR right, with C.
3. If C = 1, then return with VX ← SAR.
4. Output SR OR SAR to OUT: OUT ← SR OR SAR.
5. Input from IN.
6. If IN = 1, then go to 2.
7. Else, set SAR to SAR AND /SR: SAR ← SAR AND (NOT SR).
(Alternative: SAR SAR AND (SR EOR 1111…).
8. Go to 2.
The 1 bit, initially in C, is rotated (closed-loop shifted) right, into SR, one bit per iteration. When it returns to C (step 3 checks this), the procedure is finished. Step 4 sets the SR 1 bit in the SAR. If the comparator (IN) is high, vx is still greater than the SAR value, and this test bit remains set. If IN is low, the set bit made SAR too large, and it is cleared in step 7. Each bit, beginning with the MSB, is tested and then left set or cleared in SAR. Step 7 can use the clear-bit command for μCs that have it, with SR as the mask.
Minimal-Circuit μC-Based DACs
To reduce hardware in minimalist fashion, for slow ADCs, the DAC can be implemented as a μC-based serial DAC, as shown below.
Analog switch S3 requires a μC output-port bit. C1 and C2 are matched capacitors. A second port-bit output can implement S1 , S2 , and VR , but must have a high-impedance state, or three-state output; S1 and S2 must both be able to be set to off. The DAC reference supply, VR , uses the logic supply of the μC if S1 , S2 are implemented by a 3-state bit output from the μC. If that is not precise enough, then use two external analog switches, switched by two output-port bits.
The serial DAC algorithm, implemented in the μC, is given below, where SW is the state of S3 . OUT is the state of the C1 node, driven by S1 , S2.
0. Serial DAC
1. From MSB to LSB for n bits: SW = 0 (open)
2. OUT = bn long enough to charge C; then OUT → hi-Z (open)
3. SW = 1 long enough for charge transfer between C1 and C2 to equalize
4. Decrement n . Go to 1.
Another way to implement a simple DAC is to use a μC PWM output. Filter it through an RC integrator, where the RC time constant is much larger than the PWM switching period. The result is a constant voltage with slight PWM ripple. The PWM DAC speed is limited by the low-pass RC filter but uses only two additional, low-cost parts, R and C. For μCs without a hardware PWM generator, the PWM also can be generated in software using a timer and an output-port bit, though the cycle period will be much longer than for hardware PWMs.
μC-Based Σ- Δ ADCs
A major improvement historically over the single slope of the ramp converter was the dual-slope converter , often simplified to the modified dual-slope converter , as shown below in its non- μC instantiation. It has a minimalist appeal in that it has one analog switch, the SPST reference input switch.
Based on modified-dual-slope converter circuitry, an algorithmic variation that appeared in the late '60s was the charge-balancing or sigma-delta (Σ- Δ) (or delta-sigma ) converter. Instead of making a current-source switching decision once each measurement cycle, decisions are made every clock cycle instead, in an attempt to maintain a virtual ground at the input. The fraction of cycles requiring the opposing reference current to maintain virtual-ground “balance” gives the acquired count. A non- μC Σ- Δ circuit is shown below.
The circuit topology differs from the modified dual-slope ADC in that the flop driven by the comparator is clocked, and is a D-type flop instead of an RS flop. On a given cycle of the clock, the reference is switched in or out of the integrator to keep vo near ground. The comparator output is the sign of the error. In other words, vo is nulled by discrete-time feedback. The number of clock cycles that the flop was high, NX , over the total number of conversion counts N , is the ratio of vX /VR .
The transfer characteristic is derived by constructing the charge-balance equation for the total charge from the vX and –VR inputs to the integrator. For vo = 0, they must be equal, or
These charges are the sums of the per-cycle charges:
The total charge of each depends on the number of cycles each is integrated. Then
Substituting and solving for the measured output count,
for an n -bit counter. This result is the same as for the modified dual-slope converter.
The charge-balancing scheme has an advantage over dual-slope schemes in that its integrator output has a very small range, that of one bit of change. The dual-slope integrator output is a triangle-wave with considerable range, and the waveform slopes must remain linear to the converter resolution over the integrator range for linear conversion.
The Σ- Δ ADC is also used as a modulator for serial digital telecommunications (in CODECs) and speech processing and can be used in its μC form for these waveform-conversion applications too if the conversion rate is high enough. Parallel-feedback-derived ADCs for μCs are faster than Σ- Δ ADCs, but require more external hardware. When a minimum external-parts-count converter is all that is needed, however, the Σ- Δ ADC is hard to beat.
The next part of this article presents some minimal parts count μC-based Σ- Δ converters and software algorithms for implementing them.