Analog Product Insight

Simulator doubles the productivity of analog IP verification

The verification of analog and mixed-signal IPs can be challenging due to stringent design specifications and the steadily increasing complexity of system-on-chip (SoC) designs. That, in turn, calls for higher simulation accuracy in the verification of analog IPs such as high-speed PLLs, transceivers, and SRAMs.

When performing the verification of analog and mixed-signal IPs, Samsung Foundry also wanted to address evolving architectures, higher clock speeds, and growing SoC design sizes due to an exponential increase in layout parasitics. The fab used Cadence’s Spectre FX Simulator to address these needs for verification of PLL, SRAM, and PCI Express (PCIe) designs on the latest Samsung process nodes.

Sangyun Kim, corporate VP of Foundry Design Technology Team at Samsung Electronics, says that the Spectre FX FastSPICE Simulator has doubled the productivity on 3-nm, 4-nm and 5-nm IPs. Samsung Foundry has also leveraged the simulator to check critical measurements like PLL output average and peak-to-peak frequencies, SRAM timing checks, and PCIe transceiver output data signal. That enables engineers to ensure that the designs meet their functionality, timing, and power specifications.

Spectre FX Simulator’s scalable multicore architecture also allows verification teams to improve simulation turnaround time. “We need these simulations to run fast enough to finish within our short verification cycles without sacrificing the verification quality,” Kim said.

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