In my Single Event Effects (SEEs) with High Speed ADCs: Single Event Transient (SET) blog last month I talked a bit about single event transients with high speed ADCs. In this installment I had planned to dive into a discussion of single event upsets (SEUs). However, I’d like to take a little more time to look at SETs. There are a few more points that I’d like to cover on the topic before we move on to SEUs.
Once again, we will look at the case of the AD9246S to continue our discussion on SETs. The test setup for measuring the SET performance of that ADC is here once again for your reference. Recall that the test is performed at ambient temperature unlike the SEL test which was performed at 125o C for that part.
AD9246S Single Event Effects (SEE) Test Setup
Last month we discussed how a transient could manifest itself in the output codes of the ADC and this was illustrated in the figure AD9246S SET Error Threshold Mask which I’ve included once again here. As I pointed out it is important to understand the magnitude and length of the transient. In the case of this example a transient is shown with a length of three clock cycles and a magnitude of 6 LSBs (this could also be referred to as 64 codes).
AD9246S SET Error Threshold Mask
A similar result is shown by the plot from Run 64 for the AD9246S. In the case of Run 64 the transient has a length of two clock cycles and there are two bits of the ADC output code that are in error as noted in the ADS9246S Single Event Effects Test Report. The lower mask is approximately 0x2E80 and the output code is 0x2E74 which results in a magnitude of 12 codes.
Example Run for SET Testing – Run 64
An SET can be as little as one clock cycle in length. An upset in the output data codes of the ADC is considered an SET when the output code deviates from the expected range of values. This can occur in one clock cycle or in multiple clock cycles. An example of an SET with a length of one clock cycle is illustrated in Run 65 in the figure below. In this case the upper mask is at 0x0F14 and the output code is at approximately 0x0F20. This is once again two bits of the ADC output code that are in error as noted in the AD9246S Single Event Effects Test Report. Like the error in Run 64 these two bits of error also translate to an error magnitude of approximately 12 ADC codes.
Example Run for SET Testing – Run 65
The important aspect is to ensure that the upset can be differentiated from the code errors inherent to the ADC due to its nonlinearities. Therefore the 6 LSBs of the AD9246S are masked during the SET test run. Code errors due to irradiation in these lower bits are indistinguishable from the inherent code errors of the ADC. For the SET run a DC input was used to make the code errors easily distinguishable since the expected value is not only easy to calculate but also provide a very stable signal to the ADC that will result in an output that is also very stable. The only drawback here is that the full range of the ADC may not be completely exercised. However, this does give a good view of the errors induced by the irradiation of the device with as little impact from the inherent ADC noise as possible.
Overall the AD9246S performed very well for this test. There were very few sample errors recorded during the test as is shown in Table 3-2 of that ADC’s Single Event Effects Test Report. In addition, there error magnitudes that were observed were only 1 or 2 bits of the ADC output code in error so the magnitude of the SETs is very small. This is summarized in Table 3-3 of the ADC’s Single Event Effects Test Report. I think that sums of the SET testing for now and we can look forward to discussing single event upsets (SEUs) in the next installment. I trust that this series provides some insight into how one goes about looking at a device for the various types of SEEs. I hope you’ll join me in my next installment as we continue to look at SEEs with high speed ADCs.