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Slew limits create settling time issues in high speed amplifiers. The signal sped up, insight #16

A key metric usually reported in operational amplifier and fully differential amplifier (FDA) datasheets is settling time to some accuracy. This is a relatively difficult specification to deliver and even more difficult in end-customer applications. By definition, settling time is a step response to some final value where allowing the transition to slew limit will often vastly extend the time required to reach a final value. Let’s illustrate some simulated versus measured results for a recent high-speed voltage feedback amplifier (VFA) and highlight some test methodologies.

Theoretical vs. actual step settling performance

Because many higher speed amplifiers produce a 2nd order small signal frequency response (SSFR), we can form the basis of our investigation by using those step response metrics for the ideal step response. An idealized output step response requires an ideal input step of extremely fast edge rates. While the actual linear result might include some ringing to a final value, the exponential decay of that response envelope can be used as a simpler metric for settling time.

Figure 1 shows the academic presentation of a 2nd order DC-coupled step response. The key piece here is the envelope time constant, shown as 1/(ζ x ωn). This simplified approximate approach can then use the standard single pole settling solutions to a particular accuracy using this envelope time constant (the lower exponential in Figure 1).

Idealized 2nd order step response shows exponential decay.

Figure 1 The idealized 2nd order step response shows the exponential decay in the response envelope.

To illustrate this simplified approach to determining step settling time, we will use the high speed ADA4899 (Reference 1) VFA amplifier. The starting point will be to run an SSFR test to extract the two terms necessary for determining the envelope time constant. Figure 2 shows this gain of +1 simulation using a TINA model of the ADA4899.

Figure 2 This small signal frequency response test with a gain of +1V/V SSFR shows a 0.7dB peaking at 201Mhz with 510Mhz F-3dB.

This SSFR shape is only approximately 2nd order but can be used to estimate the necessary terms shown here as –

Fn (or Fo) = 370MHz

Q = 0.91 (or ζ = 1/(2Q) = 0.55)

Solving for the envelope time constant gives –

1/(2π x 370Mhz x 0.55) = 0.79nsec = τenv

Using this envelope time constant and the single pole solution for number of time constants (N), shown in Equation 1, the number of time constants for the 0.1% settling times specified in the ADA4899 data sheet solves to 7.09 x τenv = 5.6nsec.

Single-pole solution for N time constants
Equation 1

This predicted settling time to < 0.1% of final value only applies for a non-slew limited 2nd order output step. The maximum output step size that will not violate the device’s 310V/μsec specified (and modelled!!) slew rate can be derived using Equation 2 (Reference 2, Eq. 11), showing a maximum 0.213V ideal 2nd order step before the peak output dV/dT will exceed the modelled slew rate.

Calculation of maximum output signal that avoids exceeding device slew rate limits.
Equation 2

As will be discussed later, the best bench settling time systems use a return-to-ground input stimulus (to remove settling tails in that input stimulus). Running a 10Mhz square wave from -0.2V to 0V input will settle to a final value set by the DC error terms. The % of final value in Figure 3 shows the resulting % of final value for a square wave simulation of the model used in Figure 2.

Figure 3 The simulation for a non-slew limited -0.2V to 0V input step shows a settling time of 5.1nsec to 0.1%.

This approximate 2nd order frequency response delivers about 5.1nsec settling to within a 0.1% of final value – roughly matching the envelope model prediction of 5.6nsec.

Increasing the step size will make the device transition in and out of slew limiting on the step edge. By definition, a slew limited edge has opened the feedback loop while it transitions. An opened feedback loop risks causing internal devices to either saturate or turn off – neither of which conditions are modelled very well coming back into linearity when the loop closes again at a final value. Device models like that of the ADA4899 attempt to capture the onset of slew limiting but do less well emulating the longer recovery times that the physical device would produce when coming out of slew limiting.

Increasing the input step size to a -2V to 0V transition in the simulation circuit of Figure 2 will produce a slew limited output step as shown in the large and small signal rising edge step plots of Figure 4. Clearly, the 2V step has gone into a slew limited transition, showing a peak dV/dT of 320V/μsec very nearly matching the specified 310V/μsec slew rate.

Figure 4 A unity gain ADA4899 response to small- and large-signal step edges shows that the large signal step output is slew limited.

Zooming in on the fine scale settling time for the slew limited 2V step, in Figure 5, shows only a slight extension in “simulated” 0.1% settling time to 7.8nsec. While it is encouraging that this behavior can be simulated, this simulation for a slew limited step recovery is likely optimistic.

Figure 5 Slew limited step edge settling time simulation only shows a delay to 7.8nsec to 0.1%, much faster than the datasheet indicates.

This device datasheet (Reference 1) shows a measured 2V step settling time specification and plot in which the stimulus clearly slew limited the output in bench characterization. Both the specification and plot (Figure 6) report a much longer, 50nsec, settling time versus the simulated 7.8nsec. The measured large signal output step shows the expected slew limited ramp but not the usual overshoot for a slew limited edge. This measured 50nsec recovery to within 0.1% of final value more accurately reflects the amplifier recovery from an open loop condition on the transition. Simulated settling times for a “linear” step response can be relied upon whereas those simulations including a slew limited region are usually optimistic.

Figure 6 The datasheet’s measured unity gain 2V step response settling time (Reference 1, Figure 29) is 50nsec, much longer than the simulation predicts.

Using a slew limited output step for determining settling characteristic curves seems pretty common. Those settling times far exceed what would be expected from a linear (non-slew limited) test edge. Most slower amplifiers, like the OPA192 (Reference 3, Figure 40), seem to use slew limited large signal steps for settling time characterization as shown in Figure 7.

Figure 7 The OPA192 10V positive step settling time is delayed by slew limiting.

The measured 1.4μsec settling time to 0.01% far exceeds the TINA model simulated result of 0.92μsec. The OPA192 step simulation produces a 10V/(20V/μsec) = 500nsec slewing region and then a 420nsec recovery to within 0.01% of final value. This result is not accurately simulating the long times physically required to recover to internal bias points after the loop opens on the slewing transition.

A simple fix for this difference in characterization (or application) is to limit the output step edge rate to be lower than the available slew rate. For instance, the THS4541 FDA (Reference 4), a device with a similar 500MHz closed loop bandwidth (at gain of 2), reports a 0.1% settling time for a 2V step of 8nsec versus the 50nsec measured on the ADA4899 plot of Figure 6. But the THS4541’s characterization has also slowed the input edge to a 2nsec transition, producing a 1000V/μsec output transition that stays below the device’s rated 1500V/usec slew rate. Since the device’s loop does not open in this test, the settling to a final value is much faster than the slew limited test shown in the ADA4899 datasheet (Figure 6).

Settling time characterization considerations

Accurate bench testing of high-speed device settling time brings a number of challenges. Those include –

  • Generating as nearly as perfect an input step as possible – minimal overshoot, fast settling, and no long-term thermal tail in the input stimulus.
  • Ensuring there is nothing in the measurement path that might induce its own measured voltage perturbations – again this both a close in (in time) and long-term thermal issue.
  • Creating a well-designed DUT board that provides minimal ground current induced perturbations.

The starting point for producing the best settling time measurements is a “Flat Bottom Pulse Generator.” Early work in this area (Reference 5) identified a diode-based return-to-ground stimulus that offers a nearly perfect input test signal. In this methodology, one part of the time waveform establishes an input off of ground to produce a starting output signal for the device under test (DUT). Then, a very fast transition to a diode isolated ground input will produce a nearly perfect stimulus with no thermal tails.

Figure 8 shows one example of this approach, using a 1GHz BUF602 (Reference 6) unity gain buffer to the diode interface at its input. This unity gain buffer is only one option; others (with gain perhaps) should also be considered for their settling characteristics in delivering the stimulus waveform to the DUT. This active buffer stage is intended to provide a low impedance wideband source to the DUT – particularly useful for driving an inverting input impedance. Non-inverting, high input impedance DUT’s can likely dispense with this active buffer. The resulting <3nsec settling to a final ground value is adequate to most test needs.

Figure 8 This example of a flat bottom pulse shaper with a wideband unity gain buffer settles in <3nsec.

Most early settling time work focused on using an oscilloscope as the final measurement element. Those, of course, suffered from their own settling problems, with “false summing” (Reference 7) and gated output (Reference 8) approaches proposed to overcome scope ranging issues. These test setups also add concerns in the settling performance of all the added elements required to implement.

A much more successful approach emerged with the sampling voltage tracker (SVT) (Reference 9). The approach shown in Figure 9 slides a small sampling window across a repetitive DUT waveform iterating to a final “DC” value (at that point in time) that can then be read using the most precise DVM available. The accuracy requirements in this approach shift to needing very low jitter sources and clocks along with a very good window comparator operation.

Figure 9 This block diagram shows a sampled voltage tracker (SVT) used to characterize settling times with great precision.

Early high-speed amplifiers set out to report both close-in, fine scale settling and to fix, if possible, long term thermal tails. While close-in, fine scale settling times have remained of interest, longer term thermal tail issues have faded from view. Figure 10 show the close-in and long term (logarithmic time scale) settling plots for one of the first monolithic current feedback amplifiers (CFA) CLC400 (Reference 10), measured using an SVT.

Figure 10 The short and long-term charts of settling behavior of the 200 MHz CLC400 current feedback amplifier (CFA) use linear and log time scales.

These plots report a close-in settling to <0.01% in <15nsec with a 0.03% thermal tail effect out in the 100nsec to 1msec region. This “tail” arises from output stage induced thermal gradients shifting the input stage DC error terms over a long time period. An effort to neutralize these thermally induced effects produced the phenomenal settling performance of the CLC402 CFA device (Reference 10) shown in Figure 11.

Figure 11 Neutralization of induced thermal gradients yielded improved performance in the linear (short term) and log time (long term) settling behavior for the 150Mhz CLC402 CFA.

This SVT generated data showed a 0.0025% settling on a 2V step in 20nsec with no discernable thermal tail. Since the SVT eventually measures the voltage on a repetitive time waveform using a DVM, that 0.0025% on a 2V step was a 50uV measurement – a relatively easy (but very slow) measurement for the best DVM’s. The log time plot at that resolution required over 24hr test time. Since both of these older devices are high slew rate current feedback types, no slew limiting concerns needed addressing in the test waveform.

Obtaining the shortest settling times requires an output transition that does not cause slew limiting on the edge. Slowing the input edge rate down in test (or with input filtering in application) can be used to improve the settling times if they risk inducing slew limiting. Modern settling time measurements have likely moved on to SVT-like systems using the best recent ADC’s. For the best measurements, use a flat bottom pulse generator as an input stimulus.

Next up in this blog series: op amp noise calculations and comparisons.


  1. ADI ADA4899, “Unity Gain Stable, Ultralow Distortion, 1nV/√Hz Voltage Noise, High Speed Op Amp”
  2. EDN article “What is op amp slew rate in a slew enhanced world? Part 1 of 2”, Michael Steffes, Jan. 8, 2017,
  3. TI OPA192, “36V, Precision, Rail-to-Rail I/O, Low Offset Voltage, Low Input Bias Current, Op Amp with eTrimTM
  4. TI THS4541, “Negative Rail Input, Rail to Rail output, Precision, 850MHz Fully Differential Amplifier”
  5. National Bureau of Standards Technical Note 1067 “Reference Flat Pulse Generator”, 1983,
  6. TI BUF602, “High Speed, Closed Loop Buffer”
  7. Linear Tech. app. Note AN-10, “Methods of Measuring Op Amp Settling Time”, Jim Williams, July 1985
  8. EDN article, “Measuring wideband amplifier settling time”, Jim Williams, Aug. 12, 2010,
  9. IEEE article “Characterization of a Sampling Voltage Tracker for Measuring Fast, Repetitive Signals”, Michael Souders, et al, 1987,
  10. Comlinear CLC400, “Fast Settling, Wideband Low Gain Monolithic Op Amp”
  11. Comlinear CLC402, “Low Gain Op Amp with Fast 14-Bit Settling”,


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