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Having a circuit simulator with tons of models is a great thing. But, what do you do when you need to quickly create a new model for a component that is not in your library? Well, you could break out your Spice or VHDL-AMS modeling manual and start hand-coding your model. But wait. You are a circuit designer, not a “Supermodel-ler.” You would rather focus on getting your circuit working than spending time writing models.
What you need is an easy way to generate a simulation model that represents key component characteristics found in the component's datasheet. One way to generate such a model is to create a look table or piece-wise linear (PWL) model that computes an output (y) based on an input (x). Creating a model by hand this way can be tedious and error-prone. First, you need to look at the curve on paper, move to several points on the x-axis, draw a line up from the x-axis to where it intersects the curve, and then determine the y-value of the curve for that value of x. You copy this information to paper or a spreadsheet and then hand-enter these values into an interpolating look-up table or PWL model.
An easier, faster, and less error-prone approach would be an automated tool that would overlay the datasheet curve with an automatic curve tracing program. In this program, you would then use the mouse to select points along the curve. The program would capture the points and automatically generate the appropriate model. After capturing the curve data you should be able to define what physical relationship the curve is modeling. For example, your curve might represent such relationships as:
- Current versus voltage
- Voltage versus current
- Voltage versus time
- Current versus time
- V/I resistance curves
- I/V conductance curves
- Gain blocks and voltage limiters where current is not flowing between ports
- Voltage versus Voltage-Voltage curves where a separate port selects the curve such as a multi trace where the different curves represent different operating temperatures
Once the model has been created you can bind the model to a schematic symbol and use this custom model for simulations. The particular approach being discussed here generates custom VHDL-AMS models that can be combined with SPICE models, schematics and VHDL digital models in a unified simulation environment.
Watch a video showing you how to create your own custom VHDL-AMS models here. Then let us know if this proves useful to you.