Editor’s note: I am pleased to have Ken Coffman and his partner-in-crime in this excellent blog, Jon Dutra, Principal Electrical Engineer, Microsoft.
Being an engineer is often like being a detective. Clues are studied. Data is collected. Deductions are, uh, deduced. Pipes are smoked. No, wait, that’s Sherlock Holmes.
In this case we have a circuit that worked well at one operating point, but reliably self-destructed at another operating point. The active load circuits were the same. The transistor power dissipation was the same. The engineer pulls out his hair and cries out to the heavens: ‘What is going on?’
In this circuit, we have a pair of parallel power transistors in a constant current load, with each FET dissipating 18W. One design delivers 18A with VDS at 1V with great reliability. The modified circuit delivers 1.5A with VDS at 12V. It lets the smoke out. The power dissipation in the FETs is the same, so the failure rate should be the same, right? Not so fast, Doctor Watson.
Generally speaking, Safe Operating Area (SOA) is a poorly understood parameter. If you don’t believe us, ask your FET supplier to explain how the SOA test is performed and what the results mean in a typical design. Good luck with that.
From the FET datasheet (because we’re serious professionals, we won’t mention the vendor—wait, yes we will, it’s ST and the part number is STP27N3LH5), we see the SOA chart below with the two operating points marked with stars. Basically, what we’re saying is the green star works and the red star fails. Both stars are in the “safe” area and you’d be forgiven in thinking the red star should represent a more robust operating point. Take a minute to study the SOA plot while studiously trying to ignore the typo. What’s a Sinlge pulse? But, let’s not digress.
STP27N3LH5 SOA Plot
For this part, ST does not show the DC test result. Why is that? Is it because the DC performance was outstanding and they did not want to brag? Maybe. Maybe not, but here we are, digressing again.
What’s with the ascending line labeled with “Operation in this area is Limited by max RDS(On) ”. Beyond questionable syntax, could this note have a relation to the reliable parallel-FET performance? [Insert an image here of Jon and Ken looking at each other with puzzled expressions.]
The note means the SOA performance might be good in that area, but we’ll never know because the FET RDS(On) will not allow the control loop to drive us into that region. Put another way: the control loop will overdrive the FET gate to try to operate in that region. Aha. In the 1V@18A case, the FETs are not operating in the high-stress linear mode—their channels are either fully enhanced or close to fully enhanced and the FETs are forced into sharing current.
‘Linear mode.’ There is a phrase to strike sheer terror into the hearts of engineers. For the 12V@1.5A case, the FETs are definitely forced by the control loop into the high-stress linear mode. That’s why they fail. Shall we discuss linear mode operation in more detail? Sure, if you want us to, we will go into infinite, tedious detail in a follow-on blog.
A secondary problem is that nothing forces the red-star FETs to share current across the die. Why not? It’s common knowledge that RDS(On) increases with increasing temperature and that’s good for forcing parallel FETs to share current. So why won’t the FETs share if they are operating in the linear mode? The ST datasheet does not show this, but with increasing temperature, the VGS threshold decreases and the ΔiDrain/ ΔvGS transconductance increases. This is not good—it means the hot area of the transistor hogs more current.
This same thing happens internal to the device because one FET is actually composed of many FETs in parallel to reduce the on resistance. With low VDS voltage this increase in current does not correspond to a large relative increase in local power, but with VDS of 12 Volts the local FET temp rises a lot with the increased current, further increasing transconductance and local heating and BOOM, it gets too hot and locally fails, and now the FET is shorted.
It is interesting that the transconductance parameter does not appear in the ST data sheet. Clicking around on the web, we found that for a similar FET: if the transistor heats up by 10o C, the threshold voltage drops by about 30 mV. Recall that ID =Gm x VGS . Let’s look at these two cases. Let’s say that Gm=3 A/V and we have an on-die 33o C rise, lowering the threshold 100 mV. In the low voltage, 18 amp case, the VGS needs to be 6 volts to satisfy 18=3 x 6.
In the 12 volt VDS 1.5 amp case, we have 1.5=3 x 0.5. So the 30o C rise locally increases current, and power, by 20% in the 12VDS , low-current case and 1.6% in the high-current, low-voltage case. At some point, thermal runaway will occur. As a localized spot on the die gets hot, the threshold decreases, so it gets hotter and it hogs the current. The op amp gate driver forces the same current to flow into the smaller area and BOOM.
In the circuit that fails, what is happening? The FETs attempt to share current, but there are hotspots on the die of the failed device and the pinpoint thermal stress is incredible. How would we fix this problem? What are characteristics of FETs that work well in the linear mode? We will not answer that question here and now, but, as a hint, we will clip from an ancient Hitachi 2SK1058 FET datasheet. This old FET was notorious for good linear mode operation. Look for yourself in the SOA plot below. Would 12V@1.5A drive this FET into the RDS(On) limit area and force the FETs to share current? You probably wouldn’t use this ancient, obsolete FET in your design, but you’d try to find a modern FET with a similar characteristic.
One thing that might help is to use FETs with lower transconductance for the higher VDS case. In this way it will run with a higher VGS and the effect of thermally induced threshold shift will be reduced.
For those who know us, we love to argue. So, if you disagree, make your case in the comments section below. Otherwise, case closed, Dr. Watson. Pour the sherry.
Old School FET, the 2SK105x SOA Plot