Solutions for time interleaving ultra-high-speed analog/digital Converters at the PCB level

Synchronously sampling analog signals with time-interleaved analog/digital converters (ADCs) at billions of times per second is a considerable technical challenge, and requires very carefully designed mixed-signal circuits. In essence, the goal of time interleaving is to multiply the sampling frequency by the number of converters used, but without impacting resolution and dynamic performance.

This article explores the inherent technical challenges associated with time interleaving ADCs and provides useful system-design guidelines. New and innovative component features and design techniques that address the known issues are presented. Measured FFT results from a 7 Gsps (gigasamples per second), two-converter chip 'interleaved solution' are provided. Finally, applications-support circuitry necessary to achieve high performance is described, including clock sources and drive amplifiers.

Increasing need for higher sampling speeds
When and why is it an advantage to increase sampling frequency? There are several answers to this question. Essentially an ADC's sampling speed directly determines the instantaneous bandwidth that may be digitized in one sampling instant. The Nyquist and Shannon sampling theorems state that the maximum available sampling bandwidth (BW) is equal to half the sample frequency (Fs ).

A 3-Gsps ADC enables 1.5 GHz analog-signal spectrum to be sampled in one sampling period. Doubling the sampling speed also doubles the Nyquist bandwidth to 3 GHz. The resultant multiplication in sampling bandwidth gained by time interleaving is beneficial in many applications.

For example, radio-transceiver architectures can increase the number of information signal carriers, and therefore, system data throughput can be expanded. Increasing Fs also improves resolution in laser imaging detection and ranging (LIDAR) measurement systems, which operate on the principle of time of flight (TOF). The uncertainty in TOF measurements can be reduced by decreasing the effective sampling-clock period.

Digital oscilloscopes also require high Fs to input frequency (FIN ) ratios for accurately capturing complex analog or digital signals. Fs must be several multiples of FIN (max) to capture the harmonic components of FIN . For example, if the oscilloscope sampling frequency is not sufficiently high, a square wave will appear sinusoidal if the higher-order harmonics are outside the Nyquist bandwidth of the ADC.

Figure 1 illustrates the benefit in doubling sampling frequency in an oscilloscope front-end. The 6 Gsps sampled waveform is a much more accurate representation of the sampled analog input. Many other test instrumentation systems, such as mass spectrometers and gamma ray telescopes, depend on high over-sampling to FIN ratios for pulse-shape measurement.

Figure 1: Time-domain measured plots of a 247.77 MHz signal sampled at 3 Gsps and 6 Gsps.

(Click on image to enlarge)

There are also other advantages gained by increasing sampling frequency. Over-sampling signals also enables processing-gain benefits in the digital domain with the use of digital filtering. This is because the ADC noise floor can be spread over a larger output bandwidth. Doubling the sampling rate, for a fixed input bandwidth, results in a 3 dB improvement in dynamic range. Every further doubling of the sampling frequency provides an additional 3 dB of dynamic range.

Challenges with time interleaving
The main challenges with time interleaving are accurate phase alignment of sampling-clock edges between channels, and compensating for manufacturing variations that inherently occur between ICs. Accurately matching the gain, offset and clock phase between separate ADCs is very challenging, especially as these parameters are frequency dependant. Unless precise matching of these parameters is achieved, dynamic performance and resolution will be reduced. The three main sources of error are illustrated in Figure 2 .

Figure 2: Gain, offset and timing errors introduced by interleaving ADCs

(Click on image to enlarge)

Sampling-clock phase adjustment
Generally, a two-channel interleaved-converter system requires that the ADC input-sampling clocks are time shifted by ½ clock period. However, the National Semiconductor ADC083000 ADC architecture uses on-chip interleaving and operates with a clock frequency equal to half the sample rate, i.e. 1.5 GHz to achieve 3 Gsps. Therefore, for a two-channel system employing two ADC083000's, the ADC input sampling clock edges must be time shifted by ¼ clock period or 90° with respect to each other. This corresponds to 166.67 picoseconds for a 1.5 GHz clock.

The clock-signal trace lengths can be calculated to meet, with some accuracy, the ¼ clock-period phase shift. For FR-4 PCB material, a signal propagates at 20 cm/ns, i.e. 1 cm in 50 ps. For example, if the clock trace to one ADC is 3 cm longer than the other, this will result in a 150 ps phase shift. The challenge is to accurately meet the additional 16.67 ps time shift.

The ADC083000 has an integrated clock-phase adjustment feature that allows the user to add a delay to the input-sampling clock to shift its phase, relative to another ADC's sampling clock. The clock phase of the ADC can be adjusted manually through two internal registers over an SPI bus. The phase shift is only possible in one direction, increasing delay. The designer should determine which of two discrete ADC's is “ahead” and adjust its phase so that its sample edges are 90° between the other ADC's sample edges. Sub-picosecond adjustment resolution is provided.

Channel-to-channel gain and offset matching
In a two-converter interleaved system, the error voltages generated by channel gain mismatches result in image spurs that are located at Fs /2 – FIN and Fs /4 ± FIN (assuming the input signal is within the first Nyquist band). An 8-bit converter has 28 or 256 codes. Assuming the converter full scale input range is 1 Vp-p , the LSB size is:

1 V/256 = 3.9 mV.

We can then calculate that the required gain matching for ½ LSB accuracy is 0.2%.

The input full-scale voltage or gain of the ADC083000 can be adjusted linearly and monotonically with a 9-bit data value. The adjustment range is ???20% of the nominal 700 mVp-p differential value, or 560 mVp-p to 840 mVp-p .

840 mV – 560 mV = 280 mV.
29 = 512 steps. 280 mV/512 = 546.88 μV

This degree of fine adjustment allows greater than 0.2% gain matching as required above.

Offset mismatching between adjacent channels generates an error voltage that results in an offset spur that is located at Fs /2. Since the offset spur is located at the edge of the Nyquist band, designers of two-channel systems can typically plan their system frequency around it, and focus their efforts on gain and phase matching.

However, let us assume that the required offset matching is also ½ LSB. The input offset of the ADC083000 can be adjusted linearly and monotonically from a nominal zero offset to 45 mV of offset with 9-bit resolution. Thus, each code step provides 0.176 mV of offset and the 9-bit resolution enables ½ LSB accuracy.

Synchronization of digital outputs
Synchronizing the output data streams from both ADCs is essential to realize the combined sampling speed and bandwidth. In other words, meaningful data capture is not possible if loss of output synchronization between individual converters occurs. The gigasample-range ADCs demultiplex ('demux') the output data to reduce the digital output data rate. The user has the option of 'demuxing' the data rate by 2 or 4, depending on the data-handling capacity of the FPGA technology used.

The output capture clock (DCLK) is also divided and can be configured in SDR or DDR mode. However, demuxing introduces an additional consideration because there is now added uncertainty regarding the correspondence between the input sampling clock and the DCLK output of each ADC.

To overcome this, the ADC083000 has the capability to precisely reset its sampling clock input to a DCLK output relationship, as determined by the user-supplied DCLK_RST pulse. This allows multiple ADCs in a system to have their DCLK (and data) outputs transition at the same time with respect to the shared input clock they use for sampling, enabling the synchronization between multiple ADCs.

Digital interleaving techniques
Analog calibration is a proven method to deliver high dynamic range, and highly integrated monolithic solutions and the integrated clock phase, gain and offset adjustment features described have proven to provide a high level of accuracy.

Some potential alternatives to analog calibration techniques are digital correction algorithms that operate on the interleaved data. These engines seek to correct data converter mismatches in the digital domain without requiring any analog offset, gain, or phase correction. Ideally, these algorithms can operate independently without any calibration or prior knowledge of the input signal. Also, the time to converge on the digital offset, gain, and phase correction factors is a key system metric.

One digital post-processing engine that has been demonstrated to meet these criteria, is an algorithm developed by SP Devices, Inc. SP Devices' ADX technology continuously provides a background estimate of the gain, offset and time skew errors of the ADCs without the need for any special calibration signal or post-production trimming. This algorithm has been demonstrated to correct both static and dynamic mismatch errors.

The ADX technology estimates the error and reconstructs the signal with all mismatch errors suppressed. The error-correction algorithms of the IP-core operate effectively independent of input signal type. The result of this digital signal processing is that the time-interleaved spectrum out of the ADX core will have no apparent mismatch-related interleaving distortion spurs.

The SP Devices algorithm has been demonstrated on a reference board featuring two ADC083000 3 Gsps, 8-bit ADCs from National Semiconductor. The data converters are interleaved using the ADX technology embedded in the on-board FPGA. The block diagram of this 7 Gsps digitizer card is shown in Figure 3 .

Figure 3: Block diagram of ADQ108 system with LMX2531 and LMH6554

(Click on image to enlarge)

Figure 4 is a performance plot of the output spectrum from the SP Devices ADQ108 data acquisition card. It should be noted that that peak spurious components are due to harmonic distortion and the interleaving spurs have been dramatically reduced. (Further details on the data acquisition card can be found here.)

Figure 4: Combined ADC spectrum with ADX implemented

(Click on image to enlarge)

Ultra-high-speed ADC support circuitry
In order to achieve the high level of performance that can be attained using data converters such as the ADC083000, it is necessary to ensure that the supporting circuitry has performance comparable to the data converter itself. Key elements of support circuitry include:

1. High-performance, low-jitter clock sources
2. Highly linear, low-noise amplifiers or baluns to drive the ADC inputs

The LMX2531 or LMX2541 clock synthesizers are recommended for generating the low-jitter ADC clock signal and LMH6554 for driving the ADC analog inputs.

The LMX2531 integrates a PLL and VCO and provides a noise floor better than –160 dBc/Hz. The IC is available in several different versions to accommodate different frequency bands from 553 MHz to 2790 MHz.

For even better high-input-frequency SNR performance, the lower phase noise LMX2541 is recommended as a suitable clock source. The LMX2541 provides less than 2 milliradians (mrad) root-mean-square (rms) noise at 2.1 GHz and 3.5 mrad rms noise at 3.5 GHz. The LMX2541's PLL offers a normalized noise floor of –225 dBc/Hz and can be operated with up to 104 MHz of phase-detector rate (comparison frequency) in both integer and fractional modes.

The LMH6554 is the industry's highest-performance differential amplifier. Its low-impedance differential output is designed to drive ADC inputs and any intermediate-filter stage. This wideband, fully differential amplifier drives 8- to 16-bit high-speed ADCs with 0.1 dB gain flatness up to 800 MHz, SFDR of 72 dBc at 250 MHz, and low input-voltage noise performance of 0.9 nV/sqrt Hz.

The LMH6554 delivers 16-bit linearity up to 75 MHz when driving 2 Vp-p into loads as low as 200 Ω. With external gain-set resistors and integrated common-mode feedback, the LMH6554 can be used in differential-to-differential or single-ended-to-differential configurations. The amplifier provides large signal bandwidth up to 1.8 GHz, 8 dB noise figure and a slew rate of 6200 V/μs.

Figure 5 shows a typical block diagram implementation using the above-mentioned supporting components.

Figure 5: Typical system block diagram using high-end components

(Click on image to enlarge)

The challenges associated with interleaving high-speed ADCs and several approaches to addressing these issues have been presented. Maintaining excellent dynamic performance beyond 6 Gsps is now possible due to advancements in interleaving methodologies, low-jitter clock sources and high-performance amplifiers.

About the author
Paul McCormack is a senior applications engineer in National Semiconductor Corporation's High-Speed Signal Path Group in Europe. He received his Masters degree in Electrical and Electronic Engineering from the Queen's University of Belfast.

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