GenevaSTMicroelectronics has revealed what it says is the industry's first successful fabrication of the next-generation 65-nm serial-interface MIPHY (Multi Interface PHY) Physical Layer interface IP.
By implementing and verifying the 65-nm interface design now, ST is preparing for the migration of SoC products to 65-nm technology later this year, sharing with customers the benefit of lower power requirements and smaller physical size.
The proven IP will minimize the time-to-market for new products and reduce the development costs of new ASICs. In addition, the multiple standard capabilities (SATA Gen1, Gen2 and Gen3) of the new macro-cell will enable faster design validation for different markets and will yield the benefit of larger scale volume production while reducing costs for manufacturers by optimizing their engineering resources.
The fourth-generation MIPHY is a key IP block in ST's complete HDD IP portfolio. The device achieves a 35% reduction in die size and 30% reduction in power over the 90-nm PHY. Further architectural improvements in equalization and transmitter and receiver circuitry have resulted in enhanced jitter tolerance and lower transmit jitter.
Physical Layer macro-cells perform the high-speed serialization and de-serialization of data to and from the drive and provide a 20-bit-wide parallel interface to the link layer. In SATA applications, they can perform either host or device operations, and can dri e external signals directly without needing additional external components.
STMicroelectronics, 1-781-861 2650, www.st.com