The Current Feedback Amplifier (CFA) burst onto the scene in the mid-1980s with the commercialization of this new topology by Comlinear Corporation. It quickly propagated industrywide with many variants and feature sets. Over time, it settled into being the dominate solution for video line driving, wireline communications (xDSL, G.Hn, Powerline comms, etc), and AWG output stages. While it certainly has the same capacitive load stability issues as the high speed VFA device, the details are necessarily different given the current feedback architecture. Here, an updated Loop Gain (LG) simulation approach will be first detailed and then used to show paths into, and out of, low Phase Margin (PM) conditions.
Much like the VFA LG setup of Reference 1, we need to break the loop at the input and re-introduce the inverting node parasitic impedance to get a valid LG simulation. Here, the AC stimulus into the open loop amplifier model will be a current into the inverting node where the measurement around the loop will be the feedback current that splits off at the inverting node into the input impedance in parallel with the Rg element. Vendor simulation models vary greatly in the accuracy and feature set where some of the earlier (full transistor level) models are the best. More recent lumped element macromodels (Reference 2) can also do very well if enough attention is paid to inverting input impedance, open loop transimpedance gain Z(s), and open loop output impedance elements. While the VFA input impedance is usually in the datasheet, the CFA will often have an open loop resistance looking into the inverting input often modelled as only a resistor. This is normally adequate but, strictly speaking, there is always an inductive element in series as well.
The open loop impedance looking into a CFA inverting input (this is the output of the unity gain buffer across the inputs, Reference 3) will always be at least a series R plus an inductance in some cases. Those buffers are normally open loop with complementary emitter followers looking into the inverting node that will have an inductive characteristic at very high frequencies (>1GHz). Some unique devices, like the OPA684 and OPA683 (References 4,5), have a closed loop buffer to reduce the DC impedance looking into the inverting input. This is great for achieving a wider range of “Gain Bandwidth Independence”, but will now have a much higher equivalent inductance as the buffer loop gain rolls off. This gives a unique closed loop response shape vs. closed loop gain as shown in Figure 1 (Reference 4, front page). Here, the feedback resistor is fixed at 1kΩ and only the Rg element is varied to illustrate the relatively wide range of high bandwidth over gain that this closed loop input buffer can provide. The +3dB peaking at gain of 50V/V is unusual, but is due to the higher equivalent input inductance caused by the closed loop input buffer’s own LG rolloff.
Closed loop response vs. Gain for the OPA684
Figure 2 shows a simulation to extract that inverting input open loop impedance for the OPA684 TINA (Reference 6) model (Reference 7). Looking at the low frequency input impedance (in dBohms), and then the +3dB point from that, gives an impedance model looking into the open loop inverting input as:
- Rin = 4.3ohms
- L = 73nH
Open loop inverting input impedance for the OPA684.
With this inverting input impedance model extracted, we can now go on to set up for an overall LG simulation to test the phase margin as shown in Figure 3. This is similar to the VFA LG simulation (Reference 1) in that the loop is broken at the input with the DC operating point set by the large feedback inductor with (in this case) a test current injected through the large capacitor into the inverting input and the total loop gain traced back around to the portion of the feedback current that splits off from Rg into the open loop inverting input impedance model. Here again, the specified load for the closed loop measurement (100Ω here) is in place to include any open loop output impedance effects in the model (note, this simulation was suffering significant numerical chatter until it was changed to a Davis KLU matrix matrix solver under the “Analysis” options in TINA)
LG simulation set up to emulate closed loop gain of 50V/V condition for the OPA684.
The polarity of the feedback current sensing element plots phase margin directly and shows 43o at a LG=0dB frequency of 43MHz for this gain of 50V/V test. That 43o phase margin maps to a closed loop 3dB peaking (Figure 2, Reference 8) while the 1.6X multiplier from LG=0dB crossover to F-3dB (Figure 4, Reference 8) matches the 70MHz F-3dB at a gain of 50V/V in Figure 1.
While it is certainly gratifying to (finally) explain that +3dB peaking in the OPA684 gain of 50V/V using this LG simulation mapping to closed loop (with Figure 2,4 in Reference 8), this is probably too special a case for the much wider range of CFAs with open loop input stage buffers operating at higher quiescent current. To continue with more typical CFA designs, use the OPA691 (Reference 9) as a more representative device and model. Repeating the inverting input impedance extraction of Figure 2 for the OPA691 shows a 47Ω inverting input resistance. The normal approach (Reference 3) to holding closed loop bandwidth relatively constant over gain is to adjust the Rf value down with increasing gain (Figure 8, Reference 9). Repeating Figure 3 for the OPA691 at a gain of 2V/V will give Figure 4 showing 58o phase margin with a LG=0dB at 142MHz.
LG simulation set up to emulate closed loop gain of 2V/V condition for the OPA691.
This agrees with the minimal peaking in the measured small signal response shown in Figure 5 (page 5, Reference 9). The measured 230MHz F-3dB closely agrees with the estimated 1.6XFxover = 227MHz (Figure 4, Reference 8).
Measured small signal response over gain for the current feedback OPA691.
Now going to the recommended gain of +5V/V condition with Rf =261, the LG=0dB phase margin shows a very similar result to the gain of +2V/V LG simulation of Figure 4 explaining the close match between the gain of +2V/V and +5V/V curves in Figure 5.
LG simulation set up to test closed loop gain of +5V/V condition for the OPA691.
This simple approach to holding a fixed closed loop response vs. gain is based on the LG expression (Reference 3) given in Equation 1 where Z(s) is the open loop frequency dependent transimpedance gain from the inverting input current to the output voltage of the op amp for a given load and Rin is the open loop inverting input resistance.
Holding the feedback transimpedance (denominator in Equation 1) constant over gain is simply solving the optimum value (for about 60o phase margin) by solving Equation 2 for the required Rf as the signal gain changes. Equation 2 is showing the gain of 2V/V solution for the OPA691. Solving this for a gain of +5V/V suggests an Rf = 261Ω as shown in Figure 5.
This approach to constant closed loop bandwidth will eventually breakdown as the Rg value gets so low as to bandlimit the unity gain buffer across the inputs. Figure 7 shows a closed loop response probing the inverting pin (buffer output response) and the output for a gain of 10V/V using the OPA691 and the recommended Rf of Figure 5. The minimum Rg is usually limited to 20Ω due to this effect. Here, the buffer F-3dB at 152MHz is actually being extended by the overall loop gain to a 191MHz output F-3dB .
Normally, the buffer SSBW is >10X the overall closed loop bandwidth with higher Rg values. Repeating Figure 7 for a gain of 2 with Rf = Rg = 402Ω gives a buffer F-3dB of 4GHz.
Driving a Capacitive Load with a CFA – LG Phase Margin and Adjustments to Riso
The nominal 100Ω Rload phase margin is often in the 55 to 65o region for CFA datasheets to show a nominally flat SSBW. Adding a capacitive load usually also removes that 100Ω Rload where a typical 1kΩ sense path load is added. Most CFAs are non-RRO (with one exception, Reference 10) using various forms a complementary Class AB output stage designs. These CFA output stages have much lower output impedance than the more typical RRO stages in more recent wideband VFAs (Reference 1). There is one CFA variant using a Norton output stage that actually can use a capacitive load as a compensation element getting more stable with higher capacitive loads (Reference 11, the Exar KH560 – the lineal descendent of the original CLC560). This device constructs an output stage as fixed gain current mirrors from the inverting error current and offers a synthetic (or active) output impedance. The vast range of more typical CFA op amps offer a low open loop output impedance voltage output stage. These are resistive over a wide frequency range with usually some inductive characteristic at very high frequencies as shown in the TINA simulation of Figure 8 using the OPA691 model. Here, the low frequency open loop output impedance is only 10.7Ω.
Open loop output impedance simulation for the OPA691.
The recommended Riso vs capacitive load plots for the OPA691 are shown in Figure 9 (page 7, Reference 9). Since the CFA can hold relatively constant LG over signal gain settings, these are at a gain of +2V/V only and are not parametric on gain as the more recent VFA data sheets have shown (Reference 1).
Recommended Riso vs Capacitive Load from the OPA691 datasheet.
Setting up for the Cload = 22pF with an Riso = 40Ω in the CFA LG simulation of Figure 6, gives the 48o phase margin shown in Figure 10 with a 158MHz LG=0dB crossover. Those suggest a 2dB peaking (Figure 2, Reference 8) at the output pin with an estimated F-3dB at 253MHz (Figure 4, Reference 8).
Recommended Riso with 22pF load Loop Gain Phase Margin Simulation.
Running a closed loop simulation, and probing at both the output pin and the Cload , gives the response of Figure 11 where the response to the output pin indeed peaks 2dB with a bit higher 274MHz F-3dB while the RC pole to the load (at 180MHz) rolls that peaking off to the flat response seen at the load with the same 220MHz shown in Figure 11 as the measured response of Figure 9. Similar to the VFA investigation of Cload driving (Reference 1), the solutions here for recommended Riso are a combination of peaking to the output pin response with an RC rolloff to the Cload . The mechanisms are the same here as for the VFA device. A direct Cload creates an added pole in the loop due the open loop output impedance where adding the Riso changes that to a pole/zero pair pulling the phase shift at the output pin back up before it heads back to the inverting input to become a current feedback into the inverting input resistance of 47Ω.
Closed loop 22pF capacitive load response curves using the OPA691 model.
Increasing the Nominal Phase Margin to Reduce the Riso Required
Similar to the VFA driving a capacitive load (Reference 1) discussion, if the core amplifier can be moved to a higher initial phase margin condition prior to adding a capacitive load, a lower required Riso value should result. For a CFA, increasing the phase margin is easily accomplished by increasing the Rf feedback resistor value. This will lower the LG=0dB xover frequency – bandlimiting the device and increasing the gain for the relatively high inverting current noise for any CFA. To continue the OPA691 example, increase the Rf = Rg values to 604Ω with a 1kΩ||22pF load and check the LG phase with a much lower Riso value as shown in Figure 12. This relatively high 60o phase margin might suggest no Riso may be required. However, the local output stage circuits used for CFAs are themselves sensitive to un-isolated capacitive loads where the closed loop response with this good 60o phase margin is showing this departure from theory due to the local output stage peaking in Figure 13.
Improved phase margin gain of +2V/V LG example using the OPA691
Turning this over to a closed loop simulation shows a more involved response shape than the phase margin might suggest. This is probably coming from the local output stage peaking due to the lower Riso to the same 22pF load. This response is getting close (with 220MHz F-3dB ) to the original Rf = Rg = 402Ω from the data sheet plot in Figure 9. Tuning the nominal CFA PM by scaling the Rf and Rg appropriately can be used to reduce the required Riso if needed.
Closed loop Cload example with lower Riso due to increased Rf value.
The Effect of Capacitance on the Inverting Input to Ground for a CFA
Another quick way to lower phase margin with a CFA is to have a higher parasitic or intentional capacitance on the inverting node to an AC ground. Just like the VFA case, this adds another pole in the loop but at much higher frequencies due to the low inverting input impedance in parallel for LG analysis. Going back to the simple gain of 2 circuit with 100Ω load in Figure 4, add 20pF in parallel with the 47Ω inverting input impedance to get the LG phase margin test of Figure 14 showing only 32o phase margin.
Adding a 20pF inverting node capacitance to the OPA691 CFA LG simulation
Adding a 20pF capacitance to the closed loop gain of 2 simulation will add peaking due to both the zero in the signal gain, but also the lower loop gain phase margin as shown in Figure 14. Running this test inverting will only have the peaking due to low (but not oscillating) phase margin of approximately 6dB (Figure 2, Reference 8) at Fxover . Here, running non-inverting, shows an 18dB peaking due the combination of the peaking in the signal gain and the lower phase margin.
Closed loop gain of +2V/V with 20pF on the inverting node to ground.
It is rare that designers intentionally place a capacitance on the inverting node. But it does explain the common layout suggestion to keep the parasitic capacitance to ground and power planes as low as possible (page 20, Reference 9). Unlike the VFA, placing a compensating capacitor across the Rf element (Reference 1) will not fix this flatness issue, but will instead lead to instability as the LG test of Figure 16 shows. Since the feedback factor is essentially the feedback impedance for CFA op amps, that Cf is transitioning to zero ohms pushing the LG=0dB frequency way out to find a LG=0dB xover with more than 180o phase shift around the loop due to the higher frequency poles in the Z(s) – here showing a -25o phase margin – oscillating for sure.
Attempting to compensate the inverting capacitance with a feedback capacitance.
Adapting Common VFA Solutions to a CFA Applications
Circuits that place a capacitor across the feedback are normally heading for trouble with a CFA device. Any of those can be moved back into stability by adding the recommended feedback resistor inside the summing junction. A good example might be the dual loop Cload driver commonly used with VFA solutions (Reference 1). Just trying some values with the OPA691 driving a 1nF load gives a pretty reasonable response as shown in Figure 17. Here, a well-controlled 17MHz F-3dB is delivered by adding the required feedback resistance inside the summing junction into the inverting node over what an equivalent VFA implementation would require.
Adapting the dual loop capacitive load driver to a CFA solution.
The little frequency response bump around 100MHz suggests a bit lower phase margin. Testing this in Figure 18 shows an acceptable 34o phase margin that can be easily improved by increasing Rcomp .
LG phase margin simulation for the dual loop capacitive load driver.
This same approach to adapting VFA circuits to CFA solutions by placing the required feedback resistor inside the summing junction into the inverting input can be applied to numerous other common VFA applications circuits like the Multiple Feedback (or Rauch) active filter. While adapting a CFA to these VFA applications might vastly extend the bandwidth and slew rate available for those applications, adding that resistor for stability will also add another pair of noise terms in the Rcomp Johnson noise and the inverting current noise times that resistor.
Using an analogous LG simulation approach for the CFA to that of a VFA analysis (Reference 1) will allow a quick evaluation of the phase margin. Once the open loop inverting input impedance within the model has been extracted, the easy setups shown here will give you a quick PM extraction. The CFA has the same PM sensitivities to capacitance on the output and inverting pins as the VFA. Pre-conditioning to a higher phase margin to reduce the required Riso is done by scaling the feedback and gain resistor values up in the case of a CFA. As shown in Reference 3, a fine scale tune on the phase margin (and hence response shape) can be easily added by tuning the apparent inverting input resistor with an external R inside the summing junction to the inverting input pin. That is adjusting the feedback transimpedance in the denominator of the LG expression (Equation 1). Direct capacitive feedback is normally not used with a CFA but, if needed, can be done putting the required resistor value inside the summing junction to the inverting input. Next up – stability issues and resolutions for Fully Differential Amplifiers (FDAs).
References for CFA stability analysis and improvement
- Stability Issues and Resolutions for High Speed Voltage Feedback Op Amps, Insight #6
- TI THS3491 op amp, “900Mhz, 500mA High Power Output, Current Feedback Amplifier”
- Comlinear application note, OA-13, Michael Steffes, 1993, “Current Feedback Loop Gain Analysis and Performance Enhancement”
- TI, OPA684, “Low Power, Current Feedback Op Amp with Disable”
- TI, OPA683, “Very Low Power, Current Feedback Op Amp with Disable”
- TINA simulator available from DesignSoft for <$350 for the Basic Plus edition. Includes a wide range of vendor op amps and is the standard platform for TI op amp models.
- TINA model for the low power CFBplus current feedback op amp , OPA684
- Stability Issues for High Speed Amplifiers: Introductory Background and Improved Analysis, Insight #5
- TI, OPA691, “Low Power, Current Feedback Op Amp with Disable”
- Input and Output Voltage Range Issues for High Speed CFAs and FDAs, Insight #2
- MaxLinear, KH560, Wideband, Low Distortion, Driver Amplifier