While there has been a vast record of earlier work (ref. 1) on this topic, here we will combine a few concepts to show some emerging issues and paths to improve the Phase Margin (PM) for VFA stages that have slipped into perhaps an unsuitably low margin condition. Starting with the most ubiquitous issue of load capacitance induced problems, we will move on to how to improve that and correctly assess if indeed you are going in the right direction. What will emerge is perhaps a combination of approaches should sometimes be considered. Some of this will apply to CFAs and FDAs as well, but those also have their own special issues considered in upcoming insights.
What is the Deal with Load Capacitance Induced Phase Margin Loss?
Most op amps and FDAs (with one exception, in insight #7) will, to varying degrees, be adversely affected by parasitic or intentional load capacitance. The literature approaches this effect from a number of directions – the best I have found is to think of it in terms of what that Cload is doing with a simple open loop output resistance (Rol ) to the overall Loop Gain (LG) phase. This simple approach breaks down again with more reactive open loop Zol (Figure 6, ref. 2), but is valuable for its intuitive insight.
An unloaded VFA op amp (the 2kΩ Rload is a typical sense path load) starts out with some Loop Gain (LG) Phase Margin (PM) that can then get degraded by adding a capacitive load. Figure 1 shows this example using a relatively simple OPA725 TINA model (ref. 3) with 2 real poles in the Aol response and resistive open loop output Rol . This gain of +2V/V case using 2kΩ values is already showing what looks like a lower phase margin than a simple 90o . This is using the TINA simulator tool (ref. 4).
Gain of +2V/V closed loop response with no capacitive load.
The input capacitance in the model (9pF) is interacting with the Rf ||Rg driving impedance in the feedback network to introduce a feedback pole at 1/(2π*1kΩ*9pF) = 17.7MHz. The LG phase margin extract in Figure 2 (ref. 2) shows a LG=0dB crossover at 9.46MHz with 56o phase margin.
LG phase margin simulation including the 9pF input parasitic C in the OPA725 model.
The 1.1dB closed loop peaking in Figure 1 agrees with the expected peaking for 56o phase margin (Figure 2, ref. 2) while the 17.1MHz F-3dB is reasonably close to the expected 1.6*Fcrossover = 15.1MHz (Figure 4, ref. 2).
This simple design is already starting with a bit lower 56o phase margin before any Cload is added – which will only move the phase margin down due to the pole that will be introduced by the 112Ω open loop output impedance in this model (Figure 6, ref. 2 for setup). Adding a 100pF load does indeed raise the peaking to 6dB suggesting a phase margin near 30o (Figure 2, ref. 2). Adding a 100pF load to the Figure 2 LG simulation shows 31o phase margin.
Direct 100pF load response peaking with gain of +2V/V using the OPA725
One way to see what is happening is to set up a simulation for the signal from the output stage to the inverting node and look at the response right at the output pin as shown in Figure 4. This is the β in the LG where that direct 100pF capacitive load has introduced a pole in the β at 15MHz – which becomes a zero in the Noise Gain (NG) response. The phase of that zero in the NG ( a positive number now) is subtracted from the op amp Aol to get the LG phase. Or, equivalently, the β phase is added to the Aol phase shift.
Response at output pin with direct capacitive load.
The most common fix for phase margin loss due to capacitive loads (ref. 1d) is to add a series Riso before that Cload . This acts to change the simple pole at the output pin to a pole/zero pair pulling the phase shift back up at the output pin before the feedback signal heads back the inverting node. Since this example starts out with only 56o phase margin, adding an Riso cannot improve the phase margin beyond that. However, targeting an improvement from 31o to 45o adding an Riso before the 100pF in the LG simulation of Figure 2 shows 120Ω would be required. Starting out with an unloaded PM > 65o would allow much lower Riso values to be used as capacitive loads are added (Figure 16 below). Adding an Riso to the circuit in Figure 5 shows we have added a zero to the β phase response – it is this pulling up of the phase that makes this approach effective.
Response at output pin with Riso added before Cload
Putting Riso = 120Ω into the closed loop gain of +2V/V OPA725 circuit of Figure 6 certainly reduced the peaking where the 2.7dB peaking over the 6dB DC gain at the output pin approximately agrees with a 45o phase margin peaking (Figure 2, ref. 2). The response at Cload is now attenuated to 5.52dB DC gain by the 120Ω Riso where that simple RC reduces the peaking at the Cload to 1.6dB.
Adding an Riso to improve phase margin and reduce peaking driving a Cload .
Changing a simple pole at the output pin by adding an Riso into a pole/zero pair can also be done effectively by adding the R in series to ground with the Cload (and out of the output pin line) when that is an option. This is often seen in SAR reference line buffer designs such as Figure 7. (Figure 10, ref. 5). Here, a composite amplifier circuit using the OPA837 (ref. 6) as the output stage drives directly into the 10μF load capacitors. This OPA837 circuit also improves the capacitive load phase margin using the dual loop approach (Figure 32, ref. 7) but then adds 0.2Ω in series with each of the load caps to ground as well. Testing just this OPA837 output stage for phase margin showed 49o .
Adding series R to ground with the filter capacitors in a SAR reference buffer design.
When the load capacitance is known, and cannot endure the effects of an outside the loop Riso , the dual loop approach can be used. This technique to directly driving a capacitive load closes the loop at DC with the outer resistive loop to get gain accuracy to the capacitive load. The inner loop effectively shorts out the outer loop as the frequency increases putting the op amp in a unity NG condition with the Rx inside the loop isolating the Cload from the op amp’s open loop output impedance.
There are several descriptions of this design (ref.1c,e,f), but the simplest approach is shown in Equation 1 and 2 (from Figure 32, ref. 7). Here, a desired closed loop Butterworth F-3dB is selected to be well below the op amp Gain Bandwidth Product (GBP) and the inside the loop Rx and feedback capacitor Cf solved as shown.
Figure 8 shows an example using the OPA725 driving a 1nF load and targeting a 2.5MHz F-3dB . Running non-inverting gain of +2V/V this is approximate with its 1dB peaking and 3.1MHz F-3dB due to the 9pF parasitic input C on the inverting input. Placing a 9pF compensating capacitor across the feedback resistor flattens this response (Figure 16). Figure 8 also shows the op amp output pin is peaking even more -but the simple 1/(2πRx Cload ) pole rolls this off a bit. Using this approach, you should check your step response at the op amp output pin to confirm clipping is not occurring. If this slight peaking is not acceptable, simply increase Cf until the desired response shape is achieved and/or add a compensating capacitor across Rf (Figure 16).
Non-inverting gain of +2V/V dual loop capacitive load drive with the OPA725.
Emerging Capacitive Load Drive Issues with Newer Parts and Updated Resolutions
The Riso and dual loop approaches have been pretty standard where the latter only applies to unity gain stable VFA. So what options are available when you need to drive a capacitive load using a decompensated op amp like the recent OPA838 (ref. 8)? First, a hidden risk inside the typical Riso vs. Cload plots shown in Figure 9 (ref. 8) where the circled curve should give cause for caution. The total measured response is always a combination of whatever peaking is happening at the output pin rolled off by the 1/(2πRiso Cload ) pole. The circled curve is showing an RC rolloff at 12.2MHz that is then getting overridden by what might be significant peaking at the output pin.
Recommended Riso vs Cload parametric on gain from the OPA838 data sheet.
The fact there are different Riso curves parametric on gain in Figure 9 is another way of saying what you need to improve the phase margin depends a lot on where you are starting from. Hence, higher gain settings start out with more phase margin and will show lower required Riso for the same Cload . However, zooming in on that gain of +6V/V 100pF load curve suggesting an Riso = 130Ω, shows there is perhaps more output pin peaking than desired in Figure 10.
Closed loop gain of +6V/V with 130Ω Riso into 100pF load.
This is another instance where the peaking at the op amp output pin is much higher than the RC rolled off version measured at the Cload . Figure 11 shows the LG simulation for this where the 28o phase margin corresponds to the 6.2dB peaking in Figure 10. (Figure 2, ref. 2). The LG meter is rotated in Figure 11 to report phase margin directly. This 28o phase margin closely matches the reported 30o target in Figure 8.
LG phase margin extract for the OPA838 gain of +6V/V, 100pF load with 130Ω Riso .
This circuit is peaking at the op amp output 6dB at about 39MHz where the simple 1/(2πRiso Cload ) pole is rolling that off at 12MHz. Beware this hazard for faster parts showing a higher recommended Riso than you might expect. It is always best to run a LG phase margin test confirm adequate margin and not depend only on the final Cload response.
Shaping the Noise Gain to Higher Initial Phase Margin
Many of the older references note that operating with higher noise gain (before the Cload is added) can improve the initial phase margin and allow lower Riso . Those suggestions are normally fixed resistors or RC networks across the inputs – both increase the broadband noise. If the design can operate inverting, an older inverting compensation technique can be applied here to shape the noise gain up over frequency. This has the benefit of retaining the lower frequency loop gain, lower noise, and the higher slew rate of a decompensated device while shaping to a higher noise gain only at higher frequencies. This inverting compensation (recently rebuilt from the August 1997 original and reposted on EDN, ref. 9) can be used to shape to a higher phase margin with no load to allow lower Riso values when a capacitive load is added. Let’s set up some targets for the OPA838 and see what this will take.
- Gain = -5V/V with Rg = 400Ω, Rf = 2kΩ, Low frequency NG1 = 6 (min. specified gain)
- High frequency noise gain target NG2 = 24V/V –(1+Cs /Cf ) sets this.
- Cload = 100pF
- Riso = ??
Using the design equations below (page 12, ref. 10), and the 300MHz GBP for the 1mA OPA838 (ref. 8) , first find the Zo frequency for this nominally 2nd order Butterworth response solution – Zo is where the projection of the rising portion of the noise gain going down in frequency intersects 0dB in the Bode LG plot (ref. 9).
Zo = 357kHz
Now solve for the required capacitor across the 2kΩ feedback resistor. This is a case where the reactive open loop output impedance in the OPA838 model will interact with this feedback Cf to yield results slightly mismatching the 2nd order phase margin to Q estimates (ref. 2) as this becomes a >2nd order situation.
Cf = 9.3pF
And then to hit the higher frequency noise gain of 24V/V, add a capacitor on the inverting node to ground:
Cs = 214pF where the approximate closed loop bandwidth (before Cload is added ) will be:
F-3d B ≈ 10.4MHz where the actual increase in the noise gain due to the noise gain zero starts at (ref. 9).
NG1 *Zo = 2.14MHz.
This inverting circuit, with the compensation capacitors, is shown in Figure 12 where the resulting shape looks very close to the expected Butterworth with 11.3MHz F-3dB . Without these NG shaping caps, the closed loop response is peaking approximately 3.3dB with much higher bandwidth. The NG shaping caps are improving the phase margin at the cost of lower closed loop bandwidth.
Response shape for the gain of -5V/V with inverting compensation using the OPA838
Now, before we add a Cload and find the right Riso , run a LG simulation in Figure 13 where the Butterworth would be near 65o phase margin. The actual results show 58o phase margin due to the reactive Zol interacting with Cf – but a better place to start as the capacitive load is added and Riso resolved than the 39o implicit in the 3.3dBp peaked curve in Figure 12.
LG phase margin for the compensated circuit of Figure 12.
Going back to the closed loop circuit and adding the Cload allows a much lower (than Figure 10) Riso = 70Ω to be found that shows a more well controlled response shape at both the output pin and Cload points. Figure 14 shows the bandwidth has extended out to 18.8MHz in what is clearly more than a 2nd order response shape due to the peaking Zol in the OPA838 model.
Closed loop inverting with noise gain shaping giving lower Riso to a 100pF load.
This shaped noise gain approach appears to give an excellent response shape with the 100pF capacitive load and Riso = 70Ω. This is essentially moving the core op amp into a better phase margin place before the Riso and Cload are added and could also be applied to unity gain stable op amps if needed. It is peaking the noise gain over frequency, so check the spot noise at the output pin and capacitive load. Figure 15 shows the added simple 1/(2πRiso Cload ) pole at 23MHz is rolling off the more peaked spot noise at the op amp output pin that starts rising at the noise gain zero of 2.1MHz.
Spot output noise for inverting compensated capacitive load driver.
Improving Response Flatness for the Non-inverting Case with an Inverting Node Parasitic Pole
Of course, these two capacitors are identical topologically to the typical suggestion to improve flatness in the non-inverting case when the there is added phase shift due to capacitance on the inverting node interacting with higher Rf ||Rg source driving that node – as in Figure 1. Essentially, that suggestion (ref. 11) is setting Rg Cs = Rf Cf making the feedback β flat across frequency – exactly the same operation when tuning the flatness of a 10X scope probe.
Adding a 9pF feedback capacitor to the non-inverting gain of +2V/V of Figure 1 indeed gives a much flatter response in Figure 16. The noise gain is now flat at 6dB across frequency and the resulting closed loop response depends only on the open loop phase shift at crossover.
Non-inverting parasitic input C compensation with a feedback Cf .
Taking this updated circuit into the LG phase margin simulation now shows a very good 82o phase margin in Figure 17. At this Fcrossover of 10.8MHz, the higher pole in the OPA725 Aol model has only added 8o of added phase shift from the 90o arising from the dominant pole where the NG is now adding no phase shift.
Loop Gain (LG) phase margin with compensating feedback capacitor.
This is another technique to improve an already low phase margin in the non-inverting case before adding the capacitive load and finding Riso . With this pre-conditioning, the required Riso adding a 100pF will be much lower than the 120Ω of Figure 6. Adding the 100pF Cload and tuning Riso for 60o phase margin shows only 30Ω is now required, giving the closed loop response of Figure 18.
Lower Riso solution driving 100pF using phase margin pre-conditioning.
Another way to approach this loss of phase margin due to inverting input parasitic C issue is to constrain the resistor values to lower levels to limit this effect. As part of the resistor value solution in the Intersil (now Renesas) online non-inverting op amp design tool (ref. 12), I developed a solution (Equation 7) for the maximum Rf to limit the loss of phase margin due to the β pole back to the inverting input capacitance to < 10o .
This limit applied to the Av = 2V/V circuit for the OPA725 with Cp = 9pF and a 23MHz GBP (Figure 10, ref.2) will suggest a maximum Rf < 770Ω. Re-running a simple gain of +2V/V simulation with Rf =Rg = 750Ω will give the flat response of Figure 18 – compare this to Figure 1 with 2kΩ Rs .
Lower Rf gain of +2V/V response using the OPA725
Testing the phase margin for this yields 72o – exactly 10o lower than the perfectly equalized NG of Figure 17. This phase margin loss limit (Equation 7) was one of several constraints considered in assembling Table 1 of recommended Rf and Rg values across non-inverting gains in the OPA838 data sheet (ref. 8). Adding a Cload =100pF in Figure 19 would now require a lower Riso (than Figure 6) with Rf = Rg = 750Ω to hit a Butterworth response at the output pin.
There are many contributors to VFA closed loop phase margin. When adding a capacitive load, there are several options to tune into an improved phase margin. First, for either a non-inverting or inverting design, consider “pre-conditioning” the unloaded phase margin to a higher level to get a lower required Riso when the Cload is added as described here. Where a Cload must be driven with no Riso , consider the dual loop approach with the design equations shown here or putting that Riso in series with the load capacitor to ground where possible. Up next – stability issue and resolutions for Current Feedback Amplifiers (CFAs).
References for stability issues and resolutions for VFA op amps.
- Prior work relating to VFA capacitive load stability
- Bruce Trump “The Signal” part 12, Aug. 2013, “Why op amps oscillate: an intuitive look at two frequent causes”
- LTC Application note 148, Barry Harvey, Sept. 2014, “Does your op amp oscillate”
- TI Analogwire, Collin Wells, Aug. 2017, “Do-it-yourself: Three ways to stabilize op amp capacitive loads”
- TI Designs, Peter Semig, Timothy Claycomb, Nov. 2014, “Capacitive Load Driver Solution using an Isolation Resistor”
- ADI Ask the Applications Eng. #25, Grayson King, April 1997, “Op Amps Driving Capacitive Loads”
- ADI Ask the Applications Eng. #32, Soufiane Bendaoud, Giampaolo Marino, June 2004, “Practical Techniques to Avoid Instability Due to Capacitive Loading”
- Planet Analog article “Stability Issues for High Speed Amplifiers: Introductory Background and Improved Analysis, Insight #5”, Michael Steffes, Feb. 3, 2019, “Stability Issues for High Speed Amplifiers: Introductory Background and Improved Analysis, Insight #5”
- TINA simulation model for the OPA725
- TINA simulator available from DesignSoft for <$350 for the Basic Plus edition. Includes a wide range of vendor op amps and is the standard platform for TI op amp models.
- TI Designs, TIDA-01055, Dylan Hubbard & Taras Dudar, Sept. 15, 2017, “ADC Voltage Reference Buffer Optimization Reference Design for High-Performance DAQ Systems”
- TI OPA837 op amp, “Low Power, Precision, 105MHz, Voltage Feedback op amp”
- Burr Brown OPA627 op amp, Introduced circa 1987, “Precision High Speed Di-Fet Op Amp”
- TI OPA838 op amp, “1mA, 300MHz Gain Bandwidth, Voltage Feedback Op Amp”
- EDN article, Michael Steffes, Feb. 27, 2019, “Unique compensation technique tames high bandwidth voltage feedback op amps”
- TI OPA847 op amp, “Wideband, Ultra-Low Noise, Voltage Feedback Op Amp with Shutdown ”
- Bruce Trump “The Signal” part 13, “ Taming the oscillating op amp”
- Intersil (Renesas) (logon required). online non-inverting op amp designer