SANTA CRUZ, Calif. — Promising to bring analog IC layouts into the design cycle early, startup Accelicon Technologies Inc. has introduced a technology it calls “analog virtual prototyping.”
Accelicon's AVP product automatically generates “analog correct” transistor-level placements from schematics. It works with blocks of up to 500 transistors or so, and is integrated with Cadence Design Systems Inc.'s Virtuoso custom IC design suite.
While Accelicon has thus far stayed mostly out of public view, the company has actually been around for three years, and has a previous product called Model Quality Assurance (MQA). Sold to foundries and fabless semiconductor vendors, MQA provides Spice model library validation, comparison and documentation.
Accelicon was founded in 2002 by Xisheng Zhang, previously vice president of R&D at Celestry Design Systems Inc. The Cupertino, Calif., company employs 32, including 26 people at its R&D facility in Beijing. “The mission is to provide innovative solutions to the mixed-signal, analog and RF market,” said Tim Smith, a 12-year Cadence veteran who joined Accelicon in January 2004 as CEO.
Analog virtual prototyping, as defined by Accelicon, differs from the high-level floor-planning capabilities available in the digital IC market. An “analog virtual prototype” or “floor plan,” in Accelicon's view, is a transistor-level placement that can be generated early in the design cycle, in minutes, by circuit designers who are not layout experts.
“Today, an engineer who wishes to study the physical effects of an analog design must wait until the layout designer has finished the layout, which could take days or weeks,” Smith said. “To move to more advanced process nodes, it will be more important than ever to have an accurate analog layout early in the design cycle.”
With that layout, Smith said, a circuit designer can extract parasitic information for simulation and performance analysis. The designer can also get an accurate size estimate for the analog block and conduct “what if” analyses for various implementations. Smith said that AVP can also be used by layout teams as a “layout accelerator.”
One application for AVP is mixed-signal system-on-chip design, Smith said. He noted that it has been used to obtain layouts for blocks such as voltage-controlled oscillators, phase-locked loops and various kinds of filters.
Input to AVP includes the schematic, library information and a technology file. Accelicon uses the Cadence device library. Users may, if they wish, define their own constraints.
AVP then goes through a two-step process: circuit analysis, in which the topology is analyzed through a signal-flow- driven technique, and placement. What really differentiates AVP, Smith said, is the circuit analysis step and its ability to identify such elements as differential pairs, common centroid structures, folding resistors and “essentially all the active and passive elements in the topology.”
Once the information is known, “the placer will place along the signal path, and the algorithm will try to create devices as compact as possible,” he said.
AVP is available now priced at $50,000 for a one-year license.