Swiss researchers to describe energy-efficient devices at IEDM

LONDON — Researchers from Nanoelectronic Devices Laboratory of the Swiss Federal Institute of Technology Lausanne, Switzerland ( set to report on progress on two fundamental energy-efficient devices at the 2008 IEEE International Electron Devices Meeting (IEDM), due to run in San Francisco, Dec. 15 to 17.

The first contribution concerns an active microelectromechanical (MEMS) resonator based on a vibrating-body field effect transistor (VB-FET). This is a hybrid device that exploits the modulation of channel charge and piezoresistivity in the body of an active FET integrated on a resonant MEM structure.

The VB-FET is implemented as a n-channel silicon resonator, on a silicon-on-insulator (SOI) substrate, which is more appropriate for the fabrication of a suspended-body transistor and for a lateral device with vertical isolation.

The VB-FET always uses a combination modulation of the output: the FET channel charge modulation that is dominant at the micrometer scale, and the piezoresitivity modulation that is comparable or larger than charge modulation in smaller devices.

The EPFL VB-FET vibrates laterally rather than vertically. Like most MEMS structures the fabricated VB-FET is of micrometer scale with gaps of the order of 150-nm between the vibrating body and the lateral fixed gates.

According to EPFL, VB-FETs with double-gate and four-gate VB-FETs with resonance frequencies of 2MHz and 71MHz, respectively, exhibit built-in amplification, ultra low motional resistances and frequency tuning DC bias. This active MEMS resonator concept, with built-in amplification can achieve a negative resistance of -30 ohms, enabling the possibility of building an oscillator without any sustaining amplifier, thus reducing the power consumption and oscillator size.

The paper also demonstrates a VB-FET mixer-filter based on a single-device operating at 9.84-MHz and a VB-FET oscillator at 2.6-MHz. The VB-FET device is expected to contribute to the miniaturization and the reduction of power consumption in oscillators, mixers and filters for communications circuits.

The second paper concerns the experimental demonstration of a ferroelectric abrupt electronic switch with a sub-threshold swing better than the limit of 60mV-per-decade of MOSFET at room temperature. This minimum sub-threshold swing in conventional MOS transistors puts a fundamental lower limit on the operating voltage and the power dissipation of standards FETs.

The authors report sub-threshold swings as low as 13mV-per-decade in ferroelectric FETs with made with a 40-nm poly vinylidene fluoride trifluoroethylene (P(VDF-TrFE))over silicon dioxide gate stack.

The P(VDF-TrFE) is a dielectric layer on the top of silicon oxide with a 100-nm gold layer as the metal contact on top of this gate stack. The FET channel is silicon (n-channel enhancement-mode MOSFET).

There are many reasons for using PVDF: has a large spontaneous polarization, very good polarization stability, very low leakage due to the high resistivity. But on top of that does not require high-temperature processing (sub-200°C), is low cost and very stable, which makes it compatible with CMOS. Moreover, this creates the possibility of using it in the future for abrupt switches or non-volatile memories on flexible substrates (not only on silicon).

The mechanism governing the low subthreshold swing in Fe-FET transistors is the negative capacitance of the ferroelectric layer that can provide voltage amplification.

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