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Synopsys debuts 5 GHz PCI express core

SAN JOSE, Calif. — Synopsys officially rolls out a silicon core for PCI Express 2.0 Monday (April 28), claiming the 5 GHz technology is beginning to get attention from designers. The news comes at a time when experts say the industry is moving at a relatively slow pace down the Express road map.

Synopsys is supplying silicon intellectual property for the physical layer, controller and verification portions of the Express 2.0 spec.

“Other companies tend to have one or two of the components but not all three,” said Navraj Nandra, director of mixed-signal IP at Synopsys. “When you have to work with more than one silicon IP vendor, it gets complicated,” he said.

The IP comes in versions supporting four and eight lanes of Express, which Synopsys believes are the most common configurations. However, at least one switch maker is creating a 32-lane Express switch chip using multiple copies of the core.

The IP includes embedded diagnostics and ATE test vectors. It also supports an ability to test analog functions via a digital tester, thanks to technology Synopsys acquired with startup Accelerant Networks.

The cores currently are optimized for 2V operation in the 65nm process technology of TSMC and the Common Platform group which includes Chartered, IBM and Samsung. A version drawing 1.8V for a 40nm TSMC process will be available before the end of the year.

“It looks like most fabs are going after 40nm [and 1.8V operation] aggressively,” said Nandra.”The difference between 40 and 45nm comes down to a 19 percent savings in area for the same price,” he added.

Interest in the version 2.0 of Express is gathering steam now that a first compliance workshop for the technology has been announced for August, said Nandra. “We are starting to see a lot more request for quotes coming in for connections to server cards for storage networking and other data center functions,” he added.

The transition from the initial 2.5G version of Express to the new version will likely be a slow one, similar to the shift from PCI to Express, said Mike Krause, an I/O specialist with Hewlett-Packard's x86 server group.

“It has taken nearly four years to achieve truly broad penetration and coverage [for 2.5G Express] across the volume market segments, and it is slowly penetrating in some but not all niche market segments,” Krause wrote in an email interview. “Server adoption of Express also took quite a bit of time as many customers were satisfied with PCI and PCI-X, so phasing those technologies out completely has yet to occur,” he added.

In that light, Krause said he expects a volume ramp for the 5 GHz version in client systems will just get started this year. “In the server space, there isn't a major bandwidth bottleneck today so expect to see 5.0 be more of a 2009 start to ramp to volume and progress to broad adoption through 2010-2012,” Krause said.

Vendors may drive the speed of the transition as they gauge the trade offs between the two technologies in terms of in power consumption, throughput and efficiencies in process technologies, chip packaging and board layout, Krause said.

One of the biggest drivers for Express 2.0 is the speed with which Intel drives the technology into its mainstream processors and chip sets. Intel used Express 2.0 for the first time in a limited number of workstation and server chip sets that shipped late last year.

The Intel X38 and X48 desktop chipsets and Intel 5400 server/workstation chipsets will further proliferate the technology in high-end enterprise and consumer platforms in 2008 and beyond, said Ajay Bhatt, chief I/O architect for Intel's Digital Enterprise Group.

Looking to the horizon, the PCI Special Interest group said it is developing a 3.0 version of Express capable of up to 8G transfers/second.

“We expect that the 3.0 specifications will be available in time for the industry to develop [systems] starting in 2011 and beyond,” said Bhatt in an email exchange.

Nandra of Synopsys said he expects a draft version 0.5 of the next-generation Express spec could be completed at a PCI SIG meeting in May. He hopes Synopsys can build one serdes core that could be used for both the 8 GT/s Express 3.0 and the 10 Gbit/s speeds of the 10GBase-KR spec for backplane Ethernet.

Krause of HP agreed that the Express 3.0 spec will probably not hit until 2010-2011. Just how widely that technology is adopted depends on whether processor makers integrate it into their CPUs, he said.

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