EDA and IP vendor, Synopsys Inc. has expanded its parasitic extraction tools with analog mixed-signal (AMS) and custom digital IC designers in mind. The company has unified its Star-RCXT and Raphael NXT 3D fast field solver tool into a single environment called StarRC Custom, added some new modeling techniques and 'tuned' extraction capabilities.
Effectively a repackaging of its extraction tools, Synopsys now offers three configuration levels, as opposed to the 'one size fits all' approach. StarRC Custom is aimed at those involved in IP development, standard cells, macros and custom design. StarRC adds capabilities to handle large-capacity custom and digital designs. Finally, StarRC Ultra offers advanced sensitivity-based extraction in order to drive statistical timing or Monte Carlo analysis.
Notes Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys: “We are seeing more AMS or custom digital blocks on these large socs with each generation of product, and these blocks are growing in size. Coupled with the challenge of customers moving to advanced technology nodes, there are more details to be analysed.” He suggests that Synopsys views extraction as simply a means to an end: “The real challenge that design teams face is simulation, which is now taking much longer. Customers need both efficient extraction and simulation.” Which is why Hoogenstryd emphasises the value of newly 'optimised links between Synopsys' extraction and simulation tools.'
In the StarRC Custom flow, the designer performs regular ScanBand extraction, or uses the 3D fast field solver. To this has been added context specific device parasitic modeling, an option to include 'context' data (what is around the transistor) during the extraction step. The 'context' can affect capacitance values in advanced technology nodes. Customers can specify which devices require this accuracy-level e.g. high-speed interface designs would be candidates for this.
In StarRC and StarRC Ultra, users make use of tighter links with Synopsys' CustomSim simulation package to enable the extraction step to speed-up simulation. First among the new features is something called Selective Device Parasitic Extraction, a facility which allows the user to request the tool extracts sensitive device parasitics on a portion of the circuit, but use traditional extraction elsewhere. There's also Active Node Extraction, where net and node activity is captured when the simulation is run pre-layout. This highlights which parts of the circuits are being exercised the most; information which can be used to direct StarRC as to how to perform the circuit extraction. A third capability is called Hierarchical Back-annotation Simulation, something developed in conjunction with Synopsys' CustomSIM team, as Hoogenstryd explains: “Post-layout acceleration (PLX) feeds a tuned flat netlist of the parasitics, plus hierarchical netlist from the schematic, enabling the simulator to morph the flat data over the hierarchical data and choose where to make things flat, and where to make hierarchical.” He adds: “Customers are seeing a really good boost in simulation with this, without a loss in sign-off accuracy.”
As Hoogenstryd points out, one of StarRC Custom's first users is Synopsys' own IP development division. General release is from December 2009 onwards.