Tackling the Ever-Increasing Demand for Sideband Signaling in Mobile System Designs

Editor's note: Our guest authors are Lalan Mishra, chairman of the MIPI® Alliance Reduced Input Output Working Group and senior staff engineer, advanced connectivity technology at Qualcomm. Also Satwant Singh, vice chairman of the MIPI Alliance Reduced Input Output Working Group and senior director of strategic planning at Lattice Semiconductor. And finally, Rick Wietfeldt, chairman of the MIPI Alliance Technical Steering Group and senior director, technology at Qualcomm.

Mobile system designers often add components to smartphones, tablets and other devices to support the market’s need for more sophisticated features and new connectivity options. When pursuing these innovations, however, designers keep coming up against a fundamental mobile systems integration problem. They invariably need to increase the number of signals for sideband communications between the host processor and the peripherals, but this increases the number of general-purpose input/output (GPIO) pins along with system complexity and cost.

Acknowledging this challenge, the MIPI®Alliance in late 2014 chartered a “reduced input output” (RIO) working group to come up with a solution. Since then, experts from major semiconductor and consumer electronics industries have worked together to craft an interface specification that not only resolves the sideband proliferation issue, but also breaks new ground in the design and performance of the interface solution.

The purpose of this article is to characterize the sideband signaling challenges in mobile devices and introduce a new interface architecture created by the MIPI Alliance: the MIPI Virtual GPIO Interface (VGI). The MIPI VGI specification, currently undergoing review, is scheduled for release during the second quarter of 2016.

The Increasing Demand for Signaling Capabilities in Mobile Devices

Sideband signals are required between two system components when status and control information between the two devices must be communicated separately from the main data link. Status and control information can be transmitted at relatively low-speed and therefore designers tend to use GPIO lines for this purpose.

Several trends in the mobile device market are driving the growing demand for sideband signals. The incorporation of more radio technologies in devices is one leading trend. Today, for example, a typical device must provide cellular connectivity, Bluetooth, Wi-Fi and the emerging 60 GHz Wi-Fi standard. Each of these communications chipsets requires the use of numerous sideband GPIOs. This in turn reduces the scope of other peripheral interfaces with the main processor because GPIOs are invariably multiplexed.

As shown in Figure 1, the conventional use of GPIOs to connect components can require more than 40 GPIO lines for sideband signaling. This number of connections can have a significant impact on system design and resources. The increased number of sideband pins translates to higher package, connector and PCB costs and also increases leakage power. The availability of interface resources is also impacted because sideband signals consume precious GPIOs that otherwise could be used to interface with other peripherals.

Figure 1

I/O Utilization with Conventional GPIOs

I/O Utilization with Conventional GPIOs

Workarounds and their Drawbacks

While there are some workarounds to the sideband signaling challenge, the options have proven impractical.

Some designers use I/O expanders to augment the available GPIOs, but this drives up costs, requires extra board space and increases power requirements. Other designers tend to use a low-speed communication bus based on I2C or UART (Universal Asynchronous Receiver/Transmitter), but these alternatives may not meet all system requirements. For example, I2C and UART require a high-level operating system and software drivers, and the operating system must be up and running in order to enable the driver. This prohibits some key sideband signaling in certain situations, as when the device is not initialized or when power is lost or the peripheral loses functionality. A key requirement of VGI is to alleviate these aspects.

A New Architecture: The MIPI Virtual GPIO Interface

The MIPI Alliance RIO Working Group sought to maximize communications capability via sideband signals while minimizing the number of I/Os required (see Figure 2). The MIPI VGI achieves this goal by significantly improving throughput while reducing power requirements, among other benefits. It also introduces several new techniques that add flexibility in the architecture for use across MIPI and non-MIPI protocols.

Figure 2

I/O Reduction with the MIPI Virtual GPIO Interface

I/O Reduction with the MIPI Virtual GPIO Interface

MIPI VGI uses a finite state machine (FSM) based approach without software intervention to serialize a number of on-chip virtual GPIOs, redirected GPIOs or I/O or H/W events connecting two devices onto a 2- or 3-wire serial interface; the roadmap of future specifications for MIPI VGI will facilitate this capability on a 1-wire serial interface. These serialized GPIOs are called “virtual” because the states of the GPIOs are transmitted across the VGI interface, without requiring the same number of physical interconnects as the number of virtual GPIOs themselves.

To minimize design complexity, the working group originally considered using two data lines plus one common clock line to create a 3-wire VGI solution that included a dynamic clock frequency changing feature to meet latency and power budgets.

While VGI will support the 3-wire solution, the working group concluded that a 2-wire solution offered specific advantages in other use cases: A 2-wire solution not only saves pins on SoCs, it also saves pins on peripherals connected via connector and cable, where the cost of implementation is even greater than it is with SoCs.

The working group further evaluated various strategies to achieve the 2-wire approach and adopted several options. For example, VGI can use ring-oscillator based pulse width modulation (RO-PWM) for digital encoding, because this can lower power consumption compared to traditional PWM, which requires a phase-locked loop circuit.

To minimize data buffer depth for optimal silicon area usage and reduce latency associated with software based flow control, the working group enabled hardware flow control over the 2-wire VGI interface without impacting throughput.

To cut transmission latency in half, VGI employs a new invention, called phase-modulated pulse-width modulation (PM-PWM), which can combine two bits in one time slot to double the throughput.

Compared to traditional PWM, this new modulation scheme (an industry first) also reduces the VGI link power by half.

The modularity of the VGI architecture (see Figure 3) allows easy integration of the VGI FSM to other serial interfaces, such as UART and I2C/I3C.

Figure 3

VGI FSM Generic Integration Architecture

VGI FSM Generic Integration Architecture

VGI’s inherent flow-control ability, combined with its non-return-to-zero (NRZ) signaling, identical start/stop signaling (like that of UART) and variable frame-length support allows VGI to operate as an enhanced UART, where the requirement of request to send (RTS) and clear to send (CTS) flow control pins are eliminated.

VGI Reduces I/O Requirements

VGI offers significant, direct benefits to a product design by minimizing pins. As a comparison of Figures 1 and 2 illustrates, on a typical handheld system VGI can yield a 75% reduction in I/O pins on the SoC. A more complex system can save even more pins. As a direct byproduct of savings pins, the VGI solves a number of other important interface-related issues, including reducing silicon, packaging, board, connector and cable costs. In addition to virtualizing GPIOs on an interface, it also provides a messaging capability at improved efficiency. The VGI architecture is scalable and may be made available to other industry standards to consolidate sideband signaling techniques among organizations and reduce technology fragmentation.

Implementing MIPI VGI

Many industry groups can take advantage of this forthcoming specification. Users can include smartphone or tablet manufacturers that need to facilitate sideband signaling between radio chipsets and the application processor; companies that are connecting the processor to general peripherals such as hubs or other companion chips; manufacturers that might want their devices to interface to a docking station; or companies that manufacture low-cost I/O expanders.

When the specification is released, companies will be able to create VGI functionality by implementing VGI in silicon or instantiating the VGI framework on an external low-cost, low-power FPGA.

1 comment on “Tackling the Ever-Increasing Demand for Sideband Signaling in Mobile System Designs

  1. michaelmaloney
    August 23, 2018

    It's good to see that there are so many people who are working together to combat this problem. I can imagine that there would be a greater deal of efficiency once this system has been refined enough to roll out throughout all mobile devices and computer systems. With the networks being a little bit more dedicated and streamlined with the new components installed, I'm sure we could achieve a greater level of capability in no time.

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