Taking the ‘black magic’ out of RF design

Ultra high-speed data conversion offers many challenges to the system designer. Working with GHz analog signals is often referred to as a 'black art', so even experienced circuit designers are often hesitant when presented with such a challenge. This is truly a mixed signal environment in which all the sub circuits have to be considered carefully to allow the analog to digital converter (ADC) to deliver the optimum dynamic performance. Typical questions system designers might ask themselves are; Do I have adequate RF knowledge? Do I need to become familiar with smith chart theory again and get the charts out of the bottom drawer? What kinds of amplifiers exist with GHz bandwidth and low distortion over that entire bandwidth? How will I generate a clock signal for a GSPS converter? How can I possibility capture and process data at gigabits per second? Is my lab adequately equipped to use and evaluate such technology?

This article will explore various aspects of such designs, touching on input signal conditioning, clock generation, signal routing and data capture, and in doing so will answer the above questions. The good news is that reference designs are available that make the design of such sampling systems manageable, even without a strong RF or FPGA design background.

Gigasample converters are used in a wide variety of applications; precise measurement equipment (digital oscilloscopes, mass spectrometers, LIDAR modules), communications (point to point wireless links, wideband RADAR, satellite receivers) and scientific systems (particle detection, radio telescopes), to name a few. The architecture of these systems share common features. System performance is mostly dominated by ADC sampling speed and analog input bandwidth, and a high performance FPGA or ASIC is required for data capture. Digital oscilloscope performance is directly related to the ADC sampling rate in the analog front end. High sampling frequencies allow fast signals to be captured, displayed and analysed. ADC sampling frequency and bandwidth directly dictate the performance of wideband RADAR systems, satellite receivers and radio telescopes. The higher the conversion speed, the greater the instantaneous analog bandwidth that can be sampled.

Generally the greatest system design challenges are associated with the differential analog input circuit, the low jitter differential clock circuit and capturing and processing the high speed digital data. The latter two factors present the biggest challenge and will be dealt with here in more detail.

For the analog input circuit there are just two component choices to consider; a wideband differential amplifier or a balun transformer (the analog inputs must be driven differentially to optimise dynamic performance). A transformer is a passive component and therefore consumes no power; the input power is equal to the output power. Because transformers are passive, they generally have lower distortion than differential amplifiers. However it is more difficult to control signal path gain using a transformer while still maintaining impedance matching. Transformers also tend to suffer more from gain and phase mismatching than high performance differential amplifiers.

The advantage of choosing an amplifier is the ability to provide high gain (fixed and variable), provide DC coupling and ADC input protection. The input protection feature is necessary in some applications when the possibility exists for the voltage on the ADC inputs to exceed the maximum specified operating rating. In such cases an amplifier with an output clamping function can be very useful. The LMH6555 is a good example and the suggested configuration is shown in figure 1. Using a fast clamping diode on a transformer output is often unacceptable as the added capacitance reduces signal bandwidth and dynamic performance.

Figure 1: LMH6555 differential amp with 1.2GHz BW and 13.8dB gain

One of the most important sub-circuits within a data conversion system is the clock source. The accuracy of the clock signal directly affects the dynamic performance of the converter. The clock source must exhibit very low levels of timing jitter or phase noise. Otherwise the system dynamic performance will be poor irrespective of the quality of the front-end analog input circuitry or ADC. A perfect clock will always deliver edge transitions at precise time intervals. In practice, clock edges will arrive at continuously varying intervals. As a result of this timing uncertainty, the signal-to-noise ratio of a sampled waveform can be compromised by the data conversion process.

8- and 10-bit converters have best-case noise floors set by quantisation noise. For an N-bit ADC sampling a full-scale sinusoid, the well-known expression for SNR (in dB) is: SNR = 6.02N + 1.76. This sets the best-case noise floor for an 8-bit ADC at '49.9 dBc. The noise floor degrades from this point due to factors such as jitter on the sample clock, intrinsic aperture jitter of the ADC, spurious components arising from non-linearities in the ADC quantiser, and other internal noise such as thermal noise. As the analog input frequency increases, the requirements placed on the clock become increasingly tough. To maintain 8-bit level noise performance in the 1st Nyquist band, the clock circuit for a 3GSPS ADC must be designed so that it provides in the range of 0.5ps rms jitter. Although designing clock sources to meet such jitter performance is non trivial, a solution capable of providing such performance is shown in figure 2.

Figure 2: LMX2531 clock source provides <400fs rms jitter

The ADC08XXXX family of Gigahertz converters presented in table 1 provide a data capture clock (DCLK) that can be de-muxed and reduced to frequencies within the capability of current off-the-shelf FPGA technology. The ADC08D1520 will be used here for reference. It provides a de-multiplexed data output for each of its two channels. The ADC outputs two consecutive samples simultaneously on two 8-bit data buses (1:2 de-mux). If the ADC is configured as a single channel device and put into DES (dual-edge sampling mode), then the sampling speed is doubled (from 1.5 GSPS to 3.0 GSPS); thus, four consecutive samples are available simultaneously on each of the four buses (1:4 de-mux). This method of de-multiplexing the digital output reduces the data rate to half the sampling speed (1:2 de-mux), but doubles the number of output data bits. For cases in which ASIC technology is used that can handle the data at the full ADC sampling rate, the ADC08D1520 offers the choice of outputting the data in straight 1:1 mode.

For a 1.5 GHz sample rate, in 1:2 demux mode, the conversion data will be output synchronous to a 750 MHz clock. Even at this reduced speed, some FPGA memories and latches would not be able to accept this data directly. It is therefore beneficial to make use of a DDR method, where data is presented to the outputs on the both the rising and falling edges of the clock. Although the data rate remains the same for DDR signaling, the clock frequency is halved again to a more manageable 375 MHz. This frequency is now in the realms of the FPGA IOB data latches.

Before this data can be stored in FPGA memory, a small pipeline constructed from a series of data latches is required. Starting with the inputs, for each data line connected to an IOB pair on the FPGA, two latches will be used to capture the incoming data. One latch is clocked on the rising edge of a phase-locked data clock, while the second latch is clocked using a signal that is 180 degrees out of phase. See figure 3 for illustration. The relative position of these clocks should be adjusted so that the edges are aligned with the center of the data eye, taking into account the propagation delay of the signal as it enters the FPGA.

Figure 3: FPGA Data Capture Architecture

The Virtex-4 device is equipped with DCMs that allow these clock signals to be generated internally and can be phase-locked to the incoming data clock.
After latching the incoming data using a DCM, the clock domain must be shifted using an intermediate set of latches so that all of the data can be clocked into a memory array on the same clock edge. Because of the speed of the clock, there is not sufficient setup and hold time to re-clock the data; therefore the data must be de-multiplexed again to lower the data rate to 187.5 MHz. Once lowered, the data captured on the out-of-phase clock (even) can be re-captured using the in-phase clock (odd) running at the de-multiplexed rate. A second DCM is used to produce the de-mux clock. The clock input frequency is internally divided by two, which produces the 187.5 MHz clock signal. This DCM will provide an output that is phase-locked to the synchronous data clock (DCLK).

To aid in system debug, the ADC08D1X20 & ADC083000 devices have the capability of providing a test pattern at the four output ports completely independent of the input signal. The ADC is disengaged and a test pattern generator is connected to the outputs, including OR+/-. The test pattern output is the same in DES Mode and Non-DES Mode. Each port is given a unique 8-bit word, alternating between 1's and 0's as described in the datasheets.

This brief overview has shown there are quite a few challenges associated with designing a gigahertz sampling system. An off the shelf reference design, however, can be used to provide a fast route from idea conception to prototyping.

National provides specifications, schematic diagrams, BOMs, layout guidelines, FPGA code and application downloads to jump-start a design using National's products and tools. For example, the BIG GIG development platforms allow quick evaluation and analysis of the 500Msample/s to 3Gsample/s ADCs. Each platform includes a Xilinx Virtex-4 FPGA, which has been optimised for reduced power and superior signal integrity. For signal conditioning, the choice of a fully differential amplifier (LMH6555) or RF balun for driving the analog inputs is provided, and an on-board frequency synthesiser (LMX2531) is available for sampling clock generation, although an external clock generator can be used to offer a wider sampling clock range. The complete reference design is shown in figure 4.

Figure 4: Complete reference design, ADC08XXXX, LMH6555 & LMX2531

Each development platform interfaces with National Semiconductor's WaveVision software, which enables data capture directly to a PC. WaveVision software operates with all of National Semiconductor's data converter evaluation systems, automatically calculating FFTs and histograms, enabling inspection of sampled waveforms, and providing a range of data import and export abilities so that other industry standard evaluation tools may be used. More information can be found about WaveVision at

Just a signal source and USB cable (provided) to connect to a PC are required to get started. The WaveVision software configures each board and allows the user to configure operating modes and ADC features. The FPGA code is provided to perform the data capturing and storage as outlined above.

A JTAG port for the FPGA enables programming and debug of FPGA functions. There is also a Mictor connector that allows access to the digital data/clock stream by a logic analyser. The reference design also includes a remote diode temperature sensor (LM95221) for accurate monitoring of the ADC and FPGA die temperature.

The advantages of a development board are that it can greatly reduce development costs and time to market. The most challenging and time consuming parts of an acquisition system design, such as the ADC to FPGA interface, are provided (schematics, gerber files, FPGA code) and can be cut and pasted to any other FPGA based system, whether it be a mass spectrometer or a satellite communication system. The reference designs are designed by experienced analog and RF design engineers to obtain maximum performance from the ADC while providing maximum flexibility to the system engineer, i.e. choice of clock sources, dc and ac input coupling, access to FPGA code for further development. System engineers with little RF or FPGA design experience can quickly learn how to implement and optimise a GIG ADC system.

More information on National Semiconductors' reference design platforms can be found at

About the author:
Paul McCormack is Senior Applications Engineer at National Semiconductor's Data Conversion Division, Europe.

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