GLEN ROCK, New Jersey — Digital Blocks announced the TFT LCD Controller Reference Design centered on Digital Blocks DB9000AVLN TFT LCD Controller IP Core and Altera's FPGA Development Kits.
“The TFT LCD Controller Reference Design builds on Digital Blocks DB9000AVLN
TFT LCD Controller Verilog IP Core, as well as on Altera FPGA development kits, with their embedded NIOS II microprocessor and SDRAM and SRAM memories for program and frame buffer storage,” said Steven Stein, President of Digital Blocks. “With the reference design — which includes software — system designers can quickly bring-up a FPGA-based solution to their TFT LCD display requirements.”
The TFT LCD Controller Reference Design is available immediately for download. More information regarding the reference design can be obtained on both the Altera and Digital Blocks web site.
The DB9000AVLN IP Core targets Altera FPGAs with the NIOS II embedded processors and systems requiring a TFT LCD panel. The DB9000AVLN IP Core specifically and
cost-effectively targets TFT LCD panels with 1 or 2 Ports of 18-bit digital (6-bits/color) or 24-bit digital (8-bits/color) interface.
The DB9000AVLN IP Core contains programmable features comparable to entry-level ASSP LCD controller chips, including a color palette to reduce frame buffer space and Avalon bus bandwidth. With the cores wide range of programming parameters, the controller can support a wide range of LCD panel resolutions. Representative examples:
Square – 240×240
QVGA – 320×240, 240×320
16:9 Aspect Ratio – 480×272
VGA – 640×480
SVGA – 800×600
XGA – 1024×768
SXGA – 1280×1024
UXGA – 1600×1200