Advertisement

Blog

The 4 Most Stressful Days for an Analog IC Designer

After countless years designing analog ICs, I still stress out on four key days during a product development cycle:

  • The day the layout is sent out for first silicon
  • The day the first silicon comes back
  • The day electrostatic discharge (ESD) and latchup (LU) tests occur
  • The day high-temperature operating life (HTOL) results are in

The process of designing an analog IC starts with the specification, followed by the design, the layout, and finally releasing the layout for prototype procurement. Releasing a PCB design for prototyping is also a very stressful time, but I don't know of a PCB design that takes months until the first article arrives or that costs more than $100,000 to sample.

Once the layout is gone, it's gone. And for a few weeks to a few months, life goes back to normal — until the program manager comes over to remind you that packaged samples of the design are due back tomorrow. This prompts the second night of restless sleep as you rethink all the things that could have gone wrong.

The recovery opportunities for fixing an oversight on an IC design are nearly zero. With a PCB, perhaps a component value was wrong, or a footprint was too big. But these are easily adjusted using tricks that can be done on the bench in a minute or two. No one will be thrilled about having to fix a PCB issue, but at least it can be done immediately, and the project evaluation can continue.

On an IC, swapping or adding components is out of the question. That being said, there are limited tricks one can play if plans are made in advance.

One example is to build a resistor out of multiple composite resistors and then leave a few more resistors nearby and unconnected. If you are lucky enough to have built the problematic resistor as a composite, you can alter the resistance with the aid of lasers and sophisticated focused ion beam (FIB) equipment.

Obviously, not every component on an IC can have contingency electronics built into the design. So you do your best-effort contingency planning up front and hope for the best.

If you did a great job — not perfect, but great — your design is sufficiently functional that you can submit the packaged design for qualification. This is a multi-step process. But for an IC designer, the two most important qualification steps are testing for ESD robustness and HTOL.

An ESD test is essentially a test of what happens to the IC if someone or something that is holding an electrostatic charge touches the device pins. The test uses an electronic fixture that strikes different device pin combinations with high current and high voltage. It's similar to what would happen if you slid your feet along a carpet and then touched a doorknob.

ESD problems are rarely simple to fix. That is because the tests involve stressing signal pins with amperes of current. On an IC design, the signal conductors and components typically can handle a few hundred microamps — not amps, not even milliamps. If there is a problem, the design fix is most likely not verifiable with a 24-hour FIB circuit edit. A new layout is generally required, and so are new prototype samples.

It is usually after the device has been rendered a design success and passes ESD testing that a device's operating lifetime is assessed. This is yet another long qualification process whereby the IC is operated inside an oven with temperatures up to 150°C for several weeks. Periodically, the device is taken out of the oven and run through the final test. The requirement is not only that the device still operates, but also that the parametric shifts remain within a tight tolerance window.

A failure during HTOL testing brings everything to a halt. Not only is there a design problem, but the problem is most likely a result of a subtle change to a schematic element. Subtle changes to a circuit can be very hard to isolate. The pursuit is very much a search for “the needle in a haystack” of thousands upon thousands of components.

Alas, when the design has been verified as specification compliant, the ESD tolerance is sufficiently robust, and the operating lifetime is rendered adequate, one gets to start the whole process all over again with a new design. No matter how many times I go through this process, it is always exciting to be around the bench when power is first applied to a new silicon device.

7 comments on “The 4 Most Stressful Days for an Analog IC Designer

  1. Davidled
    December 17, 2014

    Automatic design tool could help designer simulate it in the different requirement. By using dynamic auto routing, relocation of component could be supported. Before silicon device is in the bench, IC on the PC could be fully checked like silicon device.         

  2. samicksha
    December 18, 2014

    When we think of geometrical shapes, prior to same we need be sure on CMOS technology and design rules, as this can yield good understanding on drawing.

  3. geek
    December 30, 2014

    @DaeJ: I think the stronger these automated design tools are, the easier life is getting for engineers. This also greatly reduces the chances of errors and faults in the circuit and the overall reliability gets better.

  4. geek
    December 30, 2014

    @Scott: When you're designing, how many times do you have to usually iterate between the layout and silicon stage? In other words, how many times do you have to improvise on the layout before the silicon can be worked on for any reasons?

  5. dassa.an
    December 30, 2014

    @tzbuair: Yes life of the engineers will be much more easier in the near future

  6. dassa.an
    December 30, 2014

    @tzbuair: I think it depends on the requirement itself 

  7. Scott Elder
    December 31, 2014

    @tzubair, The objective is to always have a substantially functional part with the first pass.  And then one or two tweaks on a couple layers to clean things up.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.