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The A-Z steps for building a mixed-signal SOC, Part 3: Packaging and the business plan

Editor's note : we are continuing our “dialogues” between these two distinguished engineers with this special, multipart series on the product development process. This is based on a real-life example and hands-on reality, not speculation or an academic perspective. If you want to see the rest of these dialogues, or other articles by these authors, you'll find a linked list here.)

This is Chapter Three of an ongoing series:

•to read Chapter One , click here
•to read Chapter Two , click here


[The setting : Dave Ritter has received a rare official meeting notice to join Tamara Schmitz (Dr. T) for an unspecified discussion …]

Dave Ritter: Last time we reviewed the process of defining a design. There was more to it than you expected, wasn’t there?

Tamara Schmitz: Definitely. But I still have a lingering question about the package. Do you need to know the package type to determine which components can be included within the IC?  How does it affect the design?

Dave : That’s definitely part of the process. It can be as simple as having restricted pin count or die size in a certain package, but things can get complicated.

Dr. T : I’ve read that military and space applications want to use parts with leads—which tend to have better reliability and stronger solder joints. I assume that portable applications like cell phones would want BGA (ball grid array) packages to minimize size.

Dave : Yes, and more. There are basic thermal properties that we need to know. That’s a ‘no brainer’ for a high-power part, but some signal-processing parts may dissipate almost a watt of power, and the package may be only 4mm square. In those cases we need a ‘thermally enhanced’ package which usually includes a large thermal pad in the center to conduct heat away from the chip.

For small, portable applications, BGAs may be the result of CSP: Chip Scale Packaging. In those cases the package disappears and becomes an extra processing step that puts a more robust metal layer on the chip, followed by a solder ball for each pad. In CSP, there really isn’t a package anymore, which leaves the chip vulnerable to stresses from the printed circuit card. Whether or not a CSP is appropriate depends completely on the application.

Dr. T : Are there any quick references and rules of thumb for selecting packages?

Dave : Smaller is better, as long as you can get rid of the heat. Start with the number of pins required (I like to add a couple to the original definition just “in case”), the die size required, and a list of approved packages. Just because a package exists, doesn’t mean we have approved it (run the gauntlet of tests in QA) or have the handlers to manage it in the production environment.

There are special cases, such as optical packaging for ambient light sensors. In some cases, a package is filled with a material that surrounds the chip and bond wires, improving the thermal handling of bond wires and resistance to things like vibration and mechanical shock. In an optical package, that material must be transparent, and it turns out that transparent materials may not have the same thermal expansion properties of the normal stuff. If you heat up such a package enough, it will pull the bond wires right off the chip. There’s a lot to consider.

Dr. T : Okay, let’s leave the packages for now and dive into the IC inside. There are so many questions to be answered: what process to use, how do we split up the digital or analog circuitry, which circuit topologies are appropriate, what’s our power budget, what specifications to optimize for…this is all kind of stressful….

Dave : Whoa, you’re jumping ahead of yourself. Some things are discussed before the business plan, and others are estimated from similar projects. Is this a new platform?  Or is it a modification or consolidation of existing functions?  A new platform will take longer and require more verification, proof of concept, customer buy-in, etc.  

Modification of existing functions is a lot easier. We know the basics and just have to work the new details. In either case, the marketing manager needs to estimate the amount of engineer-hours a project will take and the production costs. Is there a particularly difficult new part to the design?  Will we need to test a specification we’ve never had to?  In the end we need to estimate how much it will cost to design it (concept to first production silicon) and how much each part costs to make in production.

Dr. T : Sounds like this could include a lot of guesswork. I suspect this is where experience helps. If a marketing manager knows how long previous ICs have taken to develop and the strengths of the team they work with, I guess they can make a reasonable estimate.

Dave : Remember, too, that teams may work on similar projects. They may even be able to reuse pieces of one design in another. The catch phrase for this is “IP reuse” which stands for intellectual property. This, too, can help speed up the process of developing a new part.

Dr. T : Sounds a little like wilderness survival. You need to account for any and all potentially useful people and intelligence. These would make a big difference in deciding which ICs to pursue and develop.

Dave : You are right, but you missed one big piece—potential market. How many ICs are you going to sell, to whom are you selling and how much are you going to charge?  How long do you expect to be able to sell this IC? 

I’m no expert here, but I know my marketing colleagues are often talking about things like: TAM – total available market (how many chips of this type sell worldwide), SAM – Serviceable Available Market (how much of the TAM can we expect to supply with our new chip), ASP – Average Selling Price, and Gross Margin – how much ASP exceeds our cost per unit.  The BP has lots of charts and graphs including all of these with numbers assigned to all of them over the life of the product. It’s a bit of a mystery how they come up with all of the numbers.

Dr. T : I hear about gross margin a lot. Can you expand on that?

Dave : Gross Margin is the percentage of profit for a product. 100% would mean that we could build something for free, while 0% margin would mean we sell something for exactly what it costs us to build it. Typical gross margins are 30% in high quantities, something like 60% for newly developed high frequency products and over 90% in military or space applications.

Dr. T : How do we get 90% gross margin? 

Dave : Those parts need a lot of special design and rigorous amounts of testing to even qualify to be sold in that market. A regular part might have a datasheet 16 pages long while a specialty part might have a datasheet 1,600 pages long.

Dr. T : Oh, wait–I just found a business plan example from one of the marketing managers. It’s Table 1 .

 


Table 1. Sample business plan

Dave : That’s much easier for explaining marketing terms. Let’s go one row at a time. Total Revenue is the amount of money estimated that the company will make each year. The next is how many devices will be sold each year. The next row, average selling price, tends to decrease over the years. The next row is the cost to make the product.

Dr. T : But it is the same all the years!

Dave : Yes, but sometimes there are plans to move to a cheaper process or do a die shrink.

Dr. T : Ok.

Dave : The next row is gross margin. Since the ASP doesn’t decrease all that much and the unit cost remains the same, the gross margin doesn’t change either. Then, from the amount of revenue in the first row, we can calculate the amount of gross margin dollars. Gross margin dollars are related to profit. The first year there is a development cost of $649,000, so the overall profit is negative (equal to $405,000). After the first year, it is just profit.

Dr. T : Those last boxes look important. I know that ROI stands for “Return on Investment ”, but what does 9.4 stand for?

Dave : That means in four years, you have made 9.4 times the amount of money you have invested in the initial year. Consumer products care about shorter amounts of time like this. Industrial products may prefer to look at the ROI at 10 or 20 years. This business plan shows the potential after seven years.

Dr. T : How high does the ROI need to be to get funding?

Dave : In general, the management wants to see 10 or more to agree to the investment. It’s a lot to figure out, but the company needs to make an estimate for each product just to figure out which ones are worth pursuing.

Dr. T : Do we get to start building anything yet?  You previously showed me your prototype for MegaQ. Did you build it as part of the business plan or after?

Dave : Very interesting question. We actually did a feasibility phase of the project before the official BP. But that required us to get together and have a ‘preliminary BP’ just so we could decide to make the effort for the feasibility. Fortunately, a board-level prototype is usually a lot cheaper to develop than a chip, so the schedule and costs are a lot lower and the process was less formal.

Marketing and Applications decided it was worth the effort, and Apps had the bandwidth (me) to build it, so we went ahead and started putting together math models and PCBs. We finally got to do some soldering.

Dr. T : But for the business plan, we’d have to settle on one fabrication technology. How do we pick whether to use bipolar or CMOS and how small the geometry should be?

Dave : This could be a full discussion of its own. There are many factors. What have we used before?  We’d have verified models and the possibility of reusing circuit blocks. Would we need any special layers?

Dr. T : I’d assume the geometry would be set by what’s available and most cost-effective. If a company typically uses 0.25 micron technology, they are apt to keep using it until they need to migrate to a smaller one.

Dave : Yes. And the quick answer for bipolar versus CMOS is this. Bipolar is good at precision, low noise and high power. CMOS is low cost, good for digital and analog, and good for topologies that need switches.

Dr. T : Once we choose the technology, we’d need to know cost of a set of masks and of wafers, right?

Dave : Sometimes on complicated designs, we even include the cost to revise the top few mask layers, in case we need to debug a problem.

Dr. T : You expect to fail?

Dave : Not really. Large systems often have unforeseen behaviors. It’s practical to plan ahead. Besides, that’s not the craziest line item in the business plan. I used to work for a company that wanted the business plan to include the size of the output transistor. If we needed to increase the size, we’d have to petition the management with a new business plan.

Dr. T : That does sound crazy, but it is good to be back to talking about engineering. I’m more comfortable here. Next time let’s talk about system design, choosing circuit topologies, building models and simulation, OK?

Dave : Sure, but that discussion sounds like it’s worth at least a lunch.


About the authors
Dave Ritter was at Intersil when he co-wrote this series. 

Tamara Schmitz grew up in the Midwest, finding her way west with an acceptance letter to Stanford University. After collecting three EE degrees (BS, MS, and PhD), she taught analog circuits and test-development engineering as an assistant professor at San Jose State University. With eight years of part-time experience in applications engineering, she joined industry full-time at Intersil Corporation as a principal applications engineer

Editor's note : If you liked this article and are interested in “analog” issues such as signal input/output (sensors and transducer, real-world I/O); interfacing (level shifting, drivers/receivers); the signal chain, signal processing (op amps, filters, ADCs and DACs); and signal integrity, then go to the Planet Analog home page here for the latest in design, technology, trends, products, and news. Also, sign up for our weekly Planet Analog Newsletterhere. You won’t be disappointed, and we won’t waste your time, that's a promise!

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