The A-Z Steps for building a mixed-signal SOC, Part 5: Circuit simulation

Editor's note : we are continuing our “dialogues” between these two distinguished engineers (Dr. Tamara Schmitz and Dave Ritter) with this special, multipart series on the product development process. This is based on a real-life example and hands-on reality, not speculation or an academic perspective.

This is Chapter Five of the ongoing series; previous entries are:

Going through a mixed-signal SOC design, from A to Z

Going through a mixed-signal SOC design, from A to Z, Part 2: defining the concept

The A-Z steps for building a mixed-signal SOC, Part 3: Packaging and the business plan

The A-Z steps for building a mixed-signal SOC, Part 4: System design

Dave Ritter: Hey Dr.T, step over to the barbeque.

Tamara Schmitz: Very nice. Grilled veggies, and… what is that… salmon?

Dave: Drenched in lemons from that tree over there, plus our secret spices. It’ll be done in about 7 minutes.

Dr. T : Excellent. Just about enough time for you to continue with the silicon side of the design. Where’s the beer?

Dave: Over there in the cooler. So you probably want to know how we got started with picking a fabrication process, deciding which blocks to work on first, etc.

Dr. T : Yes. A bunch of fabrication processes are used within the company. Where do you start?

Dave: Choosing a process wasn’t too hard. CMOS is cheaper than bipolar (it has fewer layers) as long as you don’t need a lot more area to accomplish the job. Many CMOS processes are mostly about digital, but we have nice devices that help support analog. That made CMOS the logical choice.

Dr. T : “Logical,” eh?You jest…

Dave: The digital circuitry would be more compact in a smaller process, so you might think we want to choose the smallest fabrication process available.

The mixed-signal device being designed is a video equalizer

(see previous parts for details).

Dr. T : That makes sense.

Dave: Remember cost, though. 90nm, 65nm and smaller processes are more expensive, to account for the precision needed in fabrication. Also, these smaller processes have leakage which makes designing analog circuits very difficult. That makes a process in the range of 100’s of nm more appealing for the job.

Dr. T : So you trade-off quality for the analog circuits with the ability to compact the design.

Dave: Actually we started with a target package, and that gave us a max die size of about 2mm × 2mm. We wanted to allow 10% of that to be digital, and from that we could estimate the number of gates that would fit. If it was enough to build the control algorithms based on our proto work, we have a winner.

Dr. T : Which block do you start with?Roll some dice?Dart board?Rock, paper, scissors?

Dave: Not exactly. The part has almost 70dB of gain at full equalization, so noise is the critical issue. The first question was: can we build an equalizer stage (the first eq at the input) with low-enough noise? So I built up a very simple amplifier and swept the noise in the simulator.

There are a number of things to keep under control: the gm (gain) of the front end MOSFETs tells me how noisy they will be and the gm over Id term tells me how fast they transistors will run. It only took a couple of quick calculations and simulations to verify that we could get a few hundred MHz of gain BW and noise under our 2nV/ Hz target. If we met those targets, we would have performance at least as good as the prototype.

Dr. T : Okay, so now we have an equalizer stage. What’s next?

Dave: We have to control it. In the prototype this is a combination of discrete digital potentiometers and multiplexers. So I built up the equivalent in silicon and verified performance (crosstalk, bandwidth… stuff like that).

Dr. T : And how long did that take?

Dave: I think the first verification of noise and bandwidth happened in a few hours. The rest took a few weeks. I added multiple equalization stages and multiplexers to select them. There are a lot of details and verifications as you develop a complex block.

Dr. T : Like what?

Dave: Every transistor interacts with the others around it. There are bias voltages, bias currents, loading, matching and temperature effects to consider. I like to divide my system into blocks and build an equivalent model for each block according to the specifications. Then as I design each block, I can simulate with the models from the other blocks—saving simulation time.

Dr. T : So with the whole equalizer together, the rest of the stages followed in line?

Dave: Almost. I knew we needed an output amp, so we got some help with that. It’s easy to specify, but a tricky block to build in CMOS. After that I just started adding stages in order, simulating with the cable model after each addition. We had to get the equalization to work, but also keep tabs on distortion, power budgets and die area budgets.

Dr. T : Sounds like a lot to consider.

Dave: Yes, but the devil is in the details. An old timer once told me that “Paranoia is the correct state of mind” for this kind of development.

Dr. T : Woody Allen once said, “Paranoia is knowing all the facts.”

Dave: Exactly!

Dr. T : Alright, now we have all of the analog processing stages together, how do we test the whole system?

Dave: In school you just run a simulation to test for functionality. In industry, we design circuits for manufacturability. Fabrication processes have tolerances. Doping levels have ranges, and transistors can run a little fast or slow because of it. We need to simulate for the very best and very worst conditions to get the best yield of our devices.

Dr. T : I’ll bet you have to account for temperature, too. A chart of those combinations might look like this:

Dave: Good start!Now you need to account for tolerances on passive components, like resistors and capacitors. You can see how the number of cases could virtually explode and you’d never finish the design!

Dr. T : There has to be something you can do to reduce the number of simulations you need to run. Or at least to limit the dependency of a value on manufacturing tolerances.

Dave: There you go!There are a handful of design tricks you can use. One is to use resistors in ratios instead of for their exact value. Both resistors would scale larger or smaller together, so the ratio is somewhat protected. In all cases, though, we build in a little headroom (over design) to make sure we meet our targets.

Dr. T : How much do you over-design?10%?

Dave: I wish I could over-design by 10%. Usually we don’t have the space for that kind of luxury. Our original target of 2mm × 2mm and the power specifications will limit what we can achieve.

Dr. T : You haven’t mentioned anything about ESD. I understand it can be a challenge.

Dave: Actually we have experts in ESD that help us get the right cells on the correct pins. There are significant tradeoffs there also. ESD diodes have significant capacitance, and it varies with voltage, so I have to rerun distortion simulations once we apply the ESD.

Dr. T : How about testing?What do you do in design to help test the part?

Dave: For digital we have something called ‘scan’ that includes a special test mode in the logic where all the flip flops are wired in series. Running the scan test guarantees that all of the flip flops in the chain are functional. There’s a parameter called ‘coverage’ that tells us how much of the digital we actually test. It’s nice to hit over 90%.

Dr. T : What about analog testing?

Dave: In the course of the design we create a test plan that describes how each block will be tested in production. Usually that uncovers weaknesses and often results the inclusion of special test modes.

Dr. T : What kind of test modes?

Dave: Okay, here’s an easy example: we needed to know the running frequency of our internal oscillator so we invented a simple internal frequency counter based on a timing pulse sent from the tester. Basically, the tester enabled the function with one register and read back the result from another register. It was very fast and clean and saved test time.

Dr. T : Any others?

Dave: Some things are proprietary. (He says with a wink.)I need sustenance.

Dr. T : Very good. How about I trade you a beer for a chunk of that salmon?

Dave: It’s a deal!

About the authors

Tamara Schmitz grew up in the Midwest, finding her way west with an acceptance letter to Stanford University. After collecting three EE degrees (BS, MS, and PhD), she taught analog circuits and test-development engineering as an assistant professor at San Jose State University. With eight years of part-time experience in applications engineering, she joined industry full-time at Intersil Corporation as a principal applications engineer

Dave Ritter was at Intersil when he contributed to this series.

Editor's note :

If you liked this article and are interested in “analog” issues such as signal input/output (sensors and transducer, real-world I/O); interfacing (level shifting, drivers/receivers); the signal chain, signal processing (op amps, filters, ADCs and DACs); and signal integrity, then go to the Planet Analog home page here for the latest in design, technology, trends, products, and news. Also, sign up for our weekly Planet Analog Newsletter here. You won’t be disappointed, and we won’t waste your time, that's a promise!

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