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The impact of signal reflections: Part 2 in the series on lost-link bandwidth

In part 1 of this series, it was pointed out that attenuation, reflections and system noise have the potential to dramatically reduce link throughput. The first article reviewed issues surrounding attenuation. This portion will discuss the impact of reflections on link bandwidth.

Reflections in the net are the most difficult signal perturbations to control in an interface. Line losses can be managed through a combination of transmit and receive equalization techniques. Crosstalk and skew can be managed through good routing practices and careful connector selection and pin out. Ground bounce is handled in a similar fashion, assuring that an adequately low inductance path is available for the ground and power currents. Managing reflections is where the electrical engineers run squarely into the reality of mechanical engineering. A reliable contact within a connector or to a substrate requires a minimum mass and volume. Here we often have to compromise the channel signal integrity ideal in order to keep the connector from falling out of the board.

Figure 1 illustrates a typical backplane interface loaded with several cards. A signal routed from card 1 to card 6 will travel through two packages and two connectors. These will generate some reflections, but they are manageable. Connector vendors have managed to do an excellent job of impedance matching. Good packages are similarly available. Unfortunately, these connectors and packages have to be attached to boards and the signals have to be delivered to the proper routing layer. Backplane connectors generally use pin-through-hole attachment to the board, which requires vias large enough to accommodate the connector tail. Even with the solder ball attached packages, via and pad structures are still required to reach the routing layers.

Assuming the channel is routed point to point from card 1 to card 6, the signal will see six via fields associated with the packages and connectors that carry the signals. Since the channel has to be routed under four other card interfaces, the channel will also be influenced by the path through the pin fields of each of these connectors. Each of these 10 via fields represents a discontinuity on the channel interface that can degrade the received signal.


Figure 1: Typical backplane structure with numerous interfaces in the channel.


Signal carrying vias and pin fields can have a significant impact on the overall impedance profile seen by a signal. Figure 2 shows a TDR trace of 20 inches of FR-4 stripline and the resulting eye pattern at the far end of the net. This net was simulated with lossless 50-ohm lines to illustrate the impact of vias. Four pin fields and the injection and extraction of the signal through vias on the net comprise the six discontinuities. The 47 ohms dips from the pin fields reflect the capacitive loading on the signal from routing beneath connectors. The signal was routed down to the top strip line layer of an 18 layer board. The 19-ohms and 32-ohms, result from the via stubs that travel through the rest of the board thickness.


Figure 2: TDR trace and eye pattern for 20″ of lossless trace with vias at 10Gbits/s.


The routing layer for high speed signals can make a tremendous difference in the output eye. As Figure 3 shows, routing on as low a layer as possible improves the opening of the eye significantly, removing much of the capacitive stub from the signal that is associated with routing on the upper layers. Signals routed on the top strip line layer show almost complete eye closure at 10 Gbits/s, whereas those signals routed on lowest stripline layer have a horizontal opening of 0.85 UI. As stated before, the board models for these simulations were lossless to illustrate the impact of vias. A lossy environment will significantly degrade the eyes at 10 Gbits/s, requiring some of the previously discussed equalization techniques to generate usable eyes even in those signals routed in the lower layers.


Figure 3: Eye opening versus stripline routing layer assuming signal injected and extracted from the top of the board..


If high speed signals cannot be routed on the lower layers of the board, post-processing of PC boards can improve the performance significantly. Back drilling of boards to remove the excess via stubs can make previously unusable signals quite clean. Figure 3 shows the same signals on the top strip line layer as in Figure 1. In this case the via stub has been removed, resulting in a usable eye opening of 0.97 UI. As with all processing, back drilling will add cost to the board for each drill depth required.


Figure 4: TDR trace and eye pattern for 20″ of lossless trace with back drilled vias at 10Gbits/s.


Intra-Pair Differential Skew

When routing differential signals for high data rate transmission, it is paramount to closely match the true and complement legs for matched electrical delay. This skew not only lengthens the risetime at the receive end of the net, increasing the overall jitter at the reference level, but also reduces the ability of the no longer differential signal to reject common mode noise. The received signal will now be more susceptible to single-ended crosstalk from nearby signals and net currents on the reference planes. Figure 5 shows the same equalized net shown earlier in Figure 5 in Part 1 of this series . Also included is the same net with 50ps. of skew introduced. This reduces the overall height of the eye, making it more triangular, and increases the jitter from 0.066 UI to 0.200 UI. At 10 Gbits/s, 50 ps. represents half of a bit time, producing a significant stair step in the results.


Figure 5: Impact of 50 ps. of skew on 10 Gbits/s signaling.


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