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The Mystery of SAR ADC Power Specifications

One of the mysteries — or at least the cause of considerable confusion — of successive approximation register (SAR) ADCs is calculating their exact power requirements at the system level. I have found that data sheets can be a bit tricky and very frustrating on this spec.

SAR ADCs provide a low-power means to measure input signals. Very often, the power consumption scales with the sample rate, making for a very efficient measurement system. This means that, to calculate the total power consumption of the ADC, all supply pins need to be taken into account.

Typically on SAR converters, there are three potential power consuming rails: the VDD supply, the reference input, and the digital interface IO supply.

The VDD supply provides power to the analog circuitry and ADC core.

On SARs that require an external reference, the reference input is a switched capacitor input that consumes charge current during the SAR conversion bit trials. This can be a significant source of power consumption, depending on the ADC throughput rate and the size of the internal capacitor DAC. The higher the ADC throughput, the more conversion bit trials (charging of caps) and therefore more current is consumed in the capacitive DAC array.

Similarly, a larger capacitor DAC means more capacitance to charge, which results in a higher current draw. If the cap DAC is large, it may pose a problem to the reference drive circuit, and a higher-power reference circuit may be required. The same is true for the analog input, where a more powerful driving amplifier may be required to drive the higher capacitive DAC load during acquisition. Sometimes additional circuitry related to the analog input can be powered from the reference, which can further add to power consumption. Some ADCs have an internal reference buffer that gives the reference input high impedance. In this scenario, the buffer supplies the necessary reference current through another supply pin.

The digital IO supply consumes power depending on the throughput/output data rate, as well as load conditions on the data output lines. Again, higher ADC throughput means more power consumed by the digital IO, due to the higher clock rates required to transfer the converted data. Any capacitive loading on the data output lines will increase the digital IO current because of charging and discharging. In high-throughput ADCs with high clock rates, the power consumed by the digital interface can become quite significant.

Many data sheets will quote power for the VDD supply only. You have to dig into the specification table to determine the reference and digital supply power requirements. To get an accurate measure of the power consumption from a system-level perspective, all three inputs need to be considered.

It is a mystery to me why some data sheets don't take all the specs into consideration when stating a requirement as important as power consumption. Has anyone else experienced similar issues?

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6 comments on “The Mystery of SAR ADC Power Specifications

  1. goafrit2
    August 18, 2013

    >> It is a mystery to me why some data sheets don't take all the specs into consideration when stating a requirement as important as power consumption

    My understanding of many datasheet is that you get a guidance from them and not necessarily the facts or hard numbers. You must test the products to get your own metrics. It is hyper commercial marketing. People quote 18 bits chip when the ENOB, DNR and INR are not even up to the performance of 14 bits. They call it “marketing bits”. It is not a new thing – just the reflection of the influence of Wall Streets to sell more stuffs by public firms.

  2. fasmicro
    August 18, 2013

    It could be a “mystery” in SAR ADC because you have this system that needs a lot of digiatl parts to get the final bit sequence. It is the same thing with cyclic or algorithmic ADC where you need solid high performing digital systems to get the bits.  But experience engineers have ways of looking at the power budgets in block-by-block level and come up a fairly good accurate budget. SAR is a tough ADC to make and it is becoming popular with MEMS analog front ends since it offers some good tradeoffs in bits and size. Cyclic does better but you need a huge budget on digital units.

  3. Netcrawl
    August 19, 2013

    @Fasmicro Yes I agree it's still a mystery but we can solve this mystery, we only need to get the whole picture, we need to fully understand SAR ADC, their architecture and their comparison with other ADCs, I think experience is key here, it give engineers a huge advantages and tool in tackling specific problems. How can you solve the mystery If you don't understand SAR ADC specifications?  

  4. Brad_Albing
    August 23, 2013

    @goafrit2 – I would agree that the data sheet just provides guidance. You need to have the good judgment + experience to know what to do with the info provided. Where you don't know or don't have the experience, you need to enlist the help of an applications engineer from the company that made the IC.

  5. goafrit2
    September 16, 2013

    >> Where you don't know or don't have the experience, you need to enlist the help of an applications engineer from the company that made the IC

    That is wisdom. However, mastering that skill is important. Maybe, universities must be brought in line to teach and educate students on how to read and understand datasheets. Nonetheless, the key factor here is giving students skill sets to make sense of the numbers and that will come via having practical experience in making and building things

  6. Netcrawl
    September 16, 2013

    @Albing you're right experience is great plus, experience is a great teacher, gaining knowledge from work experience is probably the best teaching tool, it widen and deepen your knowledge. It provide you the ability to spot the problem quickly and solve it faster. I know people who made good things from their experience, for them experience is much better than learning inside classroom.

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