The REAL Cost for a Custom IC

There have been lots of blogs and messages lately about designing a proprietary analog IC. I wrote a blog about doing it on the cheap for $3,000. Reid Wender posted a message about prototyping 200 parts using a reconfigurable IC for $10,000.

Quite frankly, all of these cost comparisons are somewhat irrelevant. It is not about what prototyping costs — unless you ignore the other non-recurring engineering (NRE) costs, and most people can't ignore NRE unless they are doing this in their garage for the purposes of learning or experimenting. If you spend $350,000 of NRE to design a custom IC where the lifetime buy is 100,000 pieces, it doesn't cost $3 per IC. It costs $3.50 more per unit ($350,000 amortized across 100,000 units) or $6.50. So, let's change the discussion from garages to real programs and talk about the elephant in the room called NRE.

Everyone knows that major analog companies will usually pass when it comes to doing a custom IC for marginal or low quantities. This is partly because of NRE — which is certainly high and closer to $2 million, not $350,000 — but also the lost opportunities while scant resources are focused on one part for one customer. With a custom, you win or lose everything on one customer.

Before I break down the NRE elements, we have to agree on one point. A custom IC is almost always a complex system level part with many analog functions and some moderately complex digital. If this isn't true, and you could do the function with a $1 microcontroller and five $1 standard analog parts, you will be much better off just buying standard parts. Reid called this buying from Inertia Corporation.

When a brand-name analog IC company undertakes an IC development, they talk about teams, equipment resources, and materials other than the ICs. Lets talk about the team members first.

The team usually includes several people. In a small operation, the team's tasks might be divided between a small group or subcontracted out, but nevertheless, the job function/cost is still required. A typical team includes the following members:

  • A Product Definition Engineer who writes the specification. They work closely with the customer.
  • Analog Design Engineers who take the specification and design the analog portion of the IC and small digital sections. Generally, on a primarily analog part, an analog designer is the chip lead.
  • A Digital Design Engineer who writes the register transfer logic (RTL) code for digital sections that are more than 100-1000 gates.
  • A Place and Route (P&R) Engineer who takes the RTL code and generates a layout for just the digital logic gates.
  • A Top Level System Simulation Engineer whose job it is to simulate the whole mixed mode IC, including building models for the analog pieces.
  • A Layout Designer who handcrafts the IC schematic into a physical database, drops in the digital P&R, and routes up the pads and peripheral electronics. They also manage all of the design and electrical rule checks as well as comparing the schematic to the layout.
  • A Test Engineer who designs the test hardware and writes the production test program.
  • A Quality Engineer who manages the quality assurance testing of the new part such as ESD tolerance and high temperature operating life (HTOL).
  • A Product Engineer who supports the part after release to production to ensure yields, and manages customer returns.
  • An Application Engineer who is tasked with validating the part from the customer's perspective.

And finally, there is a Program Manager to oversee the IC development team, timely delivery of equipment, boards, parts, and scheduling of time on testers and burn-in ovens, etc.

While people are expensive, tools are not cheap, either. Each one of the above people use different software tools. The design tools are the most expensive, and are usually charged against a project on a time basis. Design tools, especially digital tools, can easily cost $1 million for one year.

Next in line is the hardware for evaluation, testing, and qualification. This list includes items such as applications boards, burn-in boards, ESD testing boards, and load boards for IC production testers. Burn-in boards are the most expensive, since they require one hundred or more HTOL sockets for roughly $100 a piece. Even with a metal-programmed part, you need to run full qualification just to make sure that a 2mA current is not routed with a 500μA-capable line.

And then finally there are the equipment resources, which include burn-in ovens and mixed mode IC testers. Mixed-mode testers can cost $1 million. Tester time and oven time are billed against the program.

Summarily, the team, supplies, and resources are not cheap. Mixed mode development NRE is typically measured in the millions, and consequently, the production volumes need to be in the tens of millions, otherwise the value proposition is not there. Perhaps it is possible to reduce two million to two hundred thousand, but I don't see how it can be much cheaper without taking dangerous short cuts.

If a company undertakes a custom IC development, it is an expensive endeavor fraught with lots of risk. And it is an all-or-nothing proposition. This in no way means that custom ICs make no sense. They do — but for limited purposes that need to be closely scrutinized. It's not just about what it costs to see a few parts.

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54 comments on “The REAL Cost for a Custom IC

  1. eafpres
    May 14, 2013

    Hi Scott. How ironic that as costs for practically everything drop the ability to make low volume niche parts gets harder. The tools you mention at $1M a year are software. Very sophisticated, yes. And the software guys deserve to make money (OK, at least the SW vendors you don't want to put in front of a firing squad). But $1M a year?

  2. bjcoppa
    May 14, 2013

    Most people do not realize the commoditized nature of low-end microchips, sensors and components. Many critical MEMS in cell phones have ASPs of nearly a dollar each. It is a low margin business with a low margin for error based on the cost structure. Many analog and MEMS companies benefit from purchasing former high-end fabs for what was once advanced semiconductor processing at cut-rate prices including depreciated equipment that meets their lower level tech requirements for manufacturing.

  3. Scott Elder
    May 14, 2013


    The price reflects the value.  Think about designing a digital circuit with 100,000 logic gates.  Make sure you get the timing correct, take into account the power supply droops, metal delays, etc. etc.  The problem becomes unmanageable very quickly.

    I've spent numerous hours scouring the internet for free-ware digital tools.  They are all available (like SPICE) except ones for turning RTL (digital design code) into a netlist with logic gates.  Most fab houses will do a place and route of the logic, but none want to fool with the synthesis.

    I found a link to a tool called HANA, but I've not yet figured out how to compile the code to see if it works!

    If anyone knows of freeware logic synthesis tools, please let me know!


  4. Brad Albing
    May 14, 2013

    I did wonder about the MEMS accelerometers used in cell phones regarding their cost. That expalins the business rational.

    And makes good sense if you're a start-up looking to fab some integrated analog ICs – the slightly out of date digital fab facilites.

  5. Netcrawl
    May 14, 2013

    I believe most of them are built by low cost provider based in China, they good in building things in great numbers in a very affordable. The cost is a key factor in today's mobile business, that's why we seen a lot of plant moving in China because of cost.

  6. amrutah
    May 14, 2013

    @Scott.  “If anyone knows of freeware logic synthesis tools”.

       What I have found that using free tools will take up a lot of time for setup and debug.  Also some part though user friendly, many things will be difficult to workout.

    Second thing is the no. of devices that it can handle will be less.

    I am a fan of free and open source, but for me open source=delay time to market x efficiency.

    But if one is to start a company then they can spend a few resource to get a free tool and develop for commercial purposes.


  7. amrutah
    May 14, 2013

    One factor that I see missing in the list above is the budget for the delays (be it related to design or customer issues). Usually most of the custom IC's take a few additional days/weeks then the actual schedule which should be accounted for.

  8. Scott Elder
    May 14, 2013

    Schedule delays?  Actually, that brings up an entirely new set of costs.  Since things rarely go perfect, not only is the schedule affected, but troubleshooting problems and respinning parts again adds more cost and time.  I didn't address the costs if one has to go fix problems.

  9. amrutah
    May 14, 2013

    Another thing that comes to my mind is, R & D which takes up time and lots os money.  Filing for patents will also cost the business units but if it gets approved will generate a huge ROI.


  10. eafpres
    May 14, 2013

    @Scott–I get the value based pricing thing, but that is a very slippery slope.

    In another life, a very sage sales leader told me “pigs get fat, hogs get slaughtered”.

    Makes me wonder if it is about time to cut up some hogs in the Analog IC design software business?

  11. eafpres
    May 14, 2013

    Hi analoging–Since the mobile phone market is over 1B per year, I wonder what parts you are referring to?  In some phones there is one MEMS mic and at least one accelerometer, and maybe a few other parts.  That leads quickly to a $3B to $5B market.  Not bad.  As attach rates go up, the prices must fall.  

    Let me put it this way–if your life's dream is to design and sell commodity parts for tiny margins and low ASPs, get into the mobile phone supply chain.


  12. Brad Albing
    May 14, 2013

    This seems familiar – just a variation on this theme (which we've discussed elsewhere):



  13. Brad Albing
    May 15, 2013

    Scott – you should always schedule delays. It'll save time later (I suppose the bosses from Dilbert think exactly that). Probably another blog in there regarding schedule delays, tho' not quite integrated analog related….

  14. Brad Albing
    May 15, 2013

    That's what I'm seeing here and in another section of the discussion – very high volumes sold per year, so lots of money changing hands – but at razor thin margins. I think in consideration of the larger scale integrated analog devices, that business model is not acceptable/not followed. The MEMS mic and accelerometer might be considered integrated analog devices, but just barely.

  15. goafrit2
    May 15, 2013

    >> The tools you mention at $1M a year are software. Very sophisticated, yes

    The problem is not just the acquisition cost – it is the annual licensing fees. They justify it by telling you that you need regular upgrades and annual maintenance fees take care of that.

  16. goafrit2
    May 15, 2013

    >> Most people do not realize the commoditized nature of low-end microchips, sensors and components. Many critical MEMS in cell phones have ASPs of nearly a dollar each.

    I think you are in this industry to get this right as you did. MEMS is a commodity business if you are serving 90% of the market. The only real differentiated opportunity is medical MEMS like the XLs used in pacemakers. Those ones command premium. But the ones in phones which account for the high volume, they are less than $0.90 each.

  17. goafrit2
    May 15, 2013

    >> They are all available (like SPICE) except ones for turning RTL (digital design code) into a netlist with logic gates.

    You are correct. There are indeed few companies that can do that today. And if anyone has a solution and decides to make it free, that person must be special. Digital design is driven by software. Gone were the days when people handcrafted their logics. Today, that is not an option because of the complexity of the systems.

  18. eafpres
    May 15, 2013

    Hi goafrit2–That was what I had in mind when I reacted to $1M per year.  Typical maintenance fees are 20% of purchase price.  The implication is the software costs $5M to buy plus $1M/year in fees.  That is a lot.

  19. goafrit2
    May 15, 2013

    >> And makes good sense if you're a start-up looking to fab some integrated analog ICs – the slightly out of date digital fab facilites.

    The main reason people can salvage those old fabs for MEMS is because the technology does not scale in feature size with profits. In other words, you do not need state of the art technology to make MEMS since the system is a slow one and 0.5um transistors are just good. I know many MEMS products that are still being built in 0.5um proces and they work.

  20. Scott Elder
    May 15, 2013

    FYI.  You commented yesterday about analog tool prices.  Those are the cheap tools.  The digital tools, and more specifically, synthesis and 'place and route' tools are very expensive.  And that is simply because a human can't do the same job given 100x the time.

    If you ask a layout designer (or designers) to layout a 1,000,000 gate circuit, it will cost about that same amount of money and lost sales because humans don't do anything perfect 1,000,000 times in a row.  Software tools will run all night without coffee breaks and finish without a single error as you walk in the door the next morning.

    So, here is a recommendation for aspiring engineers living in communities of the world where the cost of hardware is beyond reach.  Write some digital design tools and then sell services over the internet.  You will make a lot of money, and it only costs cheap computers and the labor of graduate students to get it started.

    In fact, here's a head start.  contact Parvez and he'll probably get you up and running with his open source Hana product.  Incidentally, last week before I wrote about Hana, the total download was 3 since last October.  This morning it is 21.  So there must be some interest.   And as Parvez wrote me, he has “..not got time to work on it for a while. It is in decent shape though, you can try it out.”

    FYI…When you finish writing the code, please remember me….SMILE.

  21. Brad Albing
    May 15, 2013

    Scott – thanks for the heads-up on Sourceforge's Hana project.

    May 15, 2013

    In all of my converations with test engineers, they are practically begging to be included earlier in the process in order to save time and have the right testing planned. (This is for software as well as hardware test.) Anyone seeing that as a trend?

  23. Scott Elder
    May 15, 2013

    Hi Janine – I hear you.  Test engineers, in analog, certainly are often looked at like Cinderella.  The best TEs I've encountered are proactive.  They join the team at the beginning, scan the design specification meticulously, ask that features be included to facilitate each required test, then sit back waiting for each design review where the designers are requested to explain how each spec is tested.  It takes a strong willed test engineer with a good historical notebook and the willingness to keep asking.  The power of record keeping can't be overstated.


  24. Brad Albing
    May 15, 2013

    Sounds right Scott. I've been in those reviews as the design engineer. I usually try to sprinkle my schematics with helpful notes and my designs with test points and jumper blocks to help the test engineer do his/her job. After all, I'll be doing that same job initially when I'm trouble-shooting my design at the prototyping stage of the design.

  25. Bonnie Baker
    May 15, 2013

    Lots of ground covered in this blog, but not the whole picture. I have had experiences with these type of “custom” products and the development, that is time to market, inevitably takes much longer than expected. That is that a 6 month promise turns into a 1 to 2 year delivery. This is because the requested product does push the envelope. What I have seen is that the customer will patiently wait past the first delay, but eventally loose interst. Basically, cut their losses.

  26. Davidled
    May 15, 2013

    I think that system is for software as well as hardware in the traditional sense. But now, in the some application, system is software, hardware and Cloud. Cloud might be tested according to Cloud engineer as new position in the future. Cloud might be associated to S/W and H/W. Cloud is never being avoided in the future.

  27. CorkICGuy
    May 16, 2013

    I agree with a lot of what is said here, but not the final conclusion necessarily. A strong motivator for doing a custom IC is to reduce the system BOM cost. Certainly in systems where you are replacing $1 standard parts, it may not make sense, but in more complex systems where you can replace several $20/$30/$40 RF & analog parts, you don't need very high volumes to show ROI on a $2M NRE. 

    Whether it's the right approach or not starts with that BOM saving v's NRE equation and if you can see ROI in a “reasonable” timeframe – reasonable is relative for each product . Once over that hurdle the advantages of doing a custom IC – its system optimised, add differentiating features, IP security etc – almost always outweigh the risks (assuming you have a trustworthy design partner).

    Increasingly OEMs have the opportunity to outsource this activity, and still retain the design (and value). See


  28. Scott Elder
    May 16, 2013


    Problems after the program starts is another entire blog or 2 by itself.  There is a reason that none of the major analog semiconductor companies have custom analog as a large part of their business model.  If it were more profitable than not, they most certainly would be involved.  Custom analog is the exception, not the rule and your observations are another reason for this.

  29. Scott Elder
    May 16, 2013

    Not sure what you meant about my “final conclusion”, but certainly custom makes sense for people like Apple Computer.  They can always find someone willing to sell $500MM worth of a custom IC for peanuts at 35% margin.  But most companies don't have that leverage.  And I doubt Apple EVER pays NRE.

    There are other cases, like medical devices where nobody wants to touch the liability issues.  Why would a $10B company put their company's assets at stake to sell a $100M company a $1 part?  The legal theory of “deep pockets” and $100MM jury verdicts keeps smart companies out of that business.  Which is why companies like Medtronics have their own IC design operations.

    Perhaps I'll write a blog about areas that do make sense.  There certainly are exception cases where the volumes are much less than $10MM.


  30. Brad Albing
    May 16, 2013

    Thanks Scott – looking forward to continued discussion in this area.

  31. Akbar Momin
    May 17, 2013

    Dear Scott,

    You can try Alliance at for digital design.

    “Alliance is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France). Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router.”

    For analog design you can try with the public domain version of old Micromagic

    “IC CAD tools, documentation, scripts, and libraries for designing
    high-performance ICs, including SUE for schematics, MAX for
    layouts, DPC for datapaths and MCC for megacells.
    Prebuilt binaries for Linux, Sparc-Solaris, and HP-PA.”

    From my 5+ year of searching free open source EDA tools with hundreads of bookmarks in my web browser i found this dream combination of EDA tools for  for a mixed-signal IC design flow.

    Unfortunately i did not have the time to test this flow in real project case. But if anybody interested, i will try to give assistance.

    Best Regards,

    Akbar Momin

    Black Forest, Germany

  32. Scott Elder
    May 17, 2013

    Thanks Akbar.  It's very kind of you to help fill out the list of open source tools.

    I knew of Alliance from the Fedora site, but I saw three problems that kept me from proceding.  (1)  The link at the Fedora site doesn't take one to the Alliance tools.  The link you provided DOES!  So great.  (2)  After hunting on the internet for a while I found an archive but the tools were from 2002–11 years ago.  So that scared me.  The link you provided shows an updated version for 2012, so that is good news.  (3) The tools are VHDL rather than Verilog, so that may be an impediment for those living in the Verilog domain.  But, hey, for free….nobody is allowed to complain, right?

    Thanks so much.  I'm going to give it a try.


  33. Akbar Momin
    May 19, 2013

    Dear Scott,

    Regarding your point#3 concern, i would recomment to use Michael Perrott's CppSim as front end tool.

    It includes all the front end for mixed-signal IC design. SUE2 for schematic entry, NGSPICE for SPICE mixed mode- mixed level circuit simulator and compiled code VERIATOR and direct ICARUS VERILOG simulator and much more…

    To bridge the gap between Verilog RTL and VHDL RTL and finally to do synthesis/P&R using Alliance tool and standard cell library from you have to translate the Verilog RTL -> VHDL RTL using freely available translators in public domain as a short time solutiion. For a long time solution the open source Alliance synthsis tool can be modified for Verilog.

    Best Regards,

    Akbar Momin



  34. goafrit2
    May 20, 2013

    >> Write some digital design tools and then sell services over the internet.

    Very good direction for getting electronics business going in the developing world. Yet, the problem is that at the end, the digital must still run on hardware. Whether it is analog or digital VLSI or embedded systems, you need an element of hardware.

  35. goafrit2
    May 20, 2013

    >> Anyone seeing that as a trend?

    I think it is a global pattern. Testers are never seen as key elements of development process despite the fact that testing consumes more than half of some production costs.

  36. goafrit2
    May 20, 2013

    >>  It takes a strong willed test engineer with a good historical notebook and the willingness to keep asking

    I am a designer and unfortunately, I hate it when testers begin to “pester” me when I am still looking for a design strategy. It is simply a human nature. The designer is there to get the product ready before deadline and most times is not worried about what will happen in three months when the chip is back from fab. Only management can make that process work.

  37. goafrit2
    May 20, 2013

    >> A strong motivator for doing a custom IC is to reduce the system BOM cost. Certainly in systems where you are replacing $1 standard parts, it may not make sense, but in more complex systems where you can replace several $20/$30/$40 RF & analog parts, you don't need very high volumes to show ROI on a $2M NRE.

    It is important you see the relationship between cost and volume. If a customer asks you to supply 1,000 units of a chip. It does not make sense to use custom ASIC as the volume is so small that you probably will not break-even. But when you run in millions, the unit cost of production drops. While the replacement makes sense, only the high volume gives you the edge.

  38. goafrit2
    May 20, 2013

    >> Cloud might be associated to S/W and H/W. Cloud is never being avoided in the future.

    It is easy to see how CS has influenced EE. When we think of cloud and how to use it in hardware development, one must still remember that you need physical things. It is like universities that want to teach EE courses over the Internet. While watching videos is cool, someone needs the scopes, the boards and kits to transfer knowledge.

  39. Brad Albing
    May 21, 2013

    I agree – we need engineers who have done actual hands-on work. I've seen a few coming right out of school who are not educated (with regard to having done lab bench work and tinkering).

  40. Brad Albing
    May 21, 2013

    Nice to see that we have so many ideas to share that they are overflowing onto LinkedIn.

  41. WKetel
    May 21, 2013

    The problem is that too many of the upper management types don't understand that not every billion gates+ analog chip comes out functioning perfectly the first time around.

    Besides that, production yields can drop.

    That is the reason that for many projects I use standard devices made by multiple sources and available from dozens of vendors, or at least several vendors. That avoids getting hurt when parts are unavailable.

  42. Via Monger
    May 21, 2013

    On the subject of low-cost mixed-signal design tools, the ViaDesigner software combines a decent set of design and simulation tools:

    • Hierarchical Schematic Capture
    • SPICE Modeling
    • Automatic Symbol Generator
    • VHDL & Verilog syntax-aware RTL Editor
    • VHDL/Verilog Digital Modeling
    • VHDL-AMS High-Level Mixed-Signal Modeling

    The ability to combine all of these design entry methods in a unified simulation environment. And, an very workable mixed-signal waveform viewer.

    ViaDesigner also comes with a set of high-level design wizards that create parameterized simulation models for useful circuits such as:

    • Op-amps: single-ended, fully differential, low noise, wideband,…
    • Programmable Gain Op-amps
    • Programmable Gain Transimpedence Amplifiers
    • Filters (continous and discrete time)
    • Integrators
    • Sigma Delta Modulators
    • ADCs & DACs
    • Linear Regulators
    • Bandgap Bias Generators, Power On Reset
    • I/O Cells
    • High-Voltage Circuits (op-amps, regulators, drivers)
    • Analog Switches,…

    ViaDesigner is not FREE.

    It costs $168/year or $19/month in case you have commitment issues. There is a Free 30-day trial available at


  43. goafrit2
    May 24, 2013

    That is an interecting link. LinkedIn needs to find better ways managing their URLs as that is not very cool enough.

  44. goafrit2
    May 24, 2013

    >> I've seen a few coming right out of school who are not educated (with regard to having done lab bench work and tinkering).

    Watch out, they are good in sims as they preach in these online schools. It is a matter of time when we will know if companies can hedge their businesses on people trained with sims who have never touched a scope or burnt a soldering iron. Educaed with certificate but no practical exposure is not the path to a great engineering future.

  45. Brad Albing
    May 24, 2013

    That link is so long, you need two browsers to make it work.

  46. Brad Albing
    May 24, 2013

    Too bad for the kids coming out of school now – but at least that means I'm still in demand as an engineer.

  47. Jonathan Jensen
    May 25, 2013

     I have been working for a custom ASIC design center for thirteen years now. Everything I have done has been customer driven – not academic. My employer fabricates and tests the ASICs as well. I have led many projects from idea stage (feasibility) to mass-production status (customer buying a lot of ICs).

    I would say a ballpark estimate for design costs are between $130 – $180 per hour of an experienced engineer (employed by a design house). Feasibility studies (where the engineer helps you write the spec.) range from 4 to 16 weeks – depending on the complexity.

    Design time may be about double to triple what the feasibility time is. Reticle costs are all over the map. If you don't mind 350nm, then reticles could be less than $5K. If you insist on 90nm, try $1000K+ or $1M+. Some fabricators support reticle sharing for prototyping. That would cut the cost by about 50-75%.

    You will more than likely need a second or even a third spin before the IC works correctly. I have seen some projects take up to 7 spins since the customer couldn't figure out how to specify what they wanted.

    Now, an example. Go to Wal-Mart and buy the cheapest clock radio you can find that has digital tuning. A cheap pocket radio with digital tuning would work too. If all that functionality were to be integrated on a 180nm ASIC you would be looking at a somewhere in the $400-$800K NRE range and about 1 year of time to mass production ready parts. No ARM processors or flash. Likely custom digital design. The final part cost would be likely less than $1.50 each in 100,000 piece quantities. You would likely have one or two design engineers working on the project.

    On the other hand, if you pick up the latest wireless router, and wanted that wrapped up in one, full custom, 90nm ASIC, be prepared to fork over $5 to $15M+ NRE to hit a 1 year cycle time. The final part cost would likely be $10 to $30 each for 100,000 piece quantities. You would likely have 10 to 15 design engineers working on the project.

    I have to chuckle inside because this blog topic reminds me of what used to happen to me when my family discovered that I “made chips” for a living.  They would come up to me and tell me about an idea they had for a chip and wondered if I could make one for them.  I said certainly — for around $500,000.  I don't get off-the-wall requests any more.


  48. Brad Albing
    May 25, 2013

    Jonathan – thanks for a well thought out and well expressed point of view on the topic. Stand by for responses.

  49. goafrit2
    June 3, 2013

    >> I would say a ballpark estimate for design costs are between $130 – $180 per hour of an experienced engineer (employed by a design house).

    That is very expensive. The model now is to design with guys in U.S. and get people in India to implement. If you do that with your layout guys in India, your cost will drop to around $40/hr.

  50. goafrit2
    June 3, 2013

    Great insight on his comments and he is indeed very experienced in this business. Yet, the real summary is that when you have big volume, ASIC is the way to go. If not, you need to find alternatives. Now that foundries are very expensive which means companies have to outsource production, that makes it more difficult. You need volume to have a teeth in this game.

  51. CarlWH
    June 19, 2013

    The first question I always get asked, is “What will it cost”?

    A brief search on the web will see many figures banded about from a few thousand to many millions of dollars. But this is true of any market, you will always have a spread of pricing and what it comes down to is what do you want and why, and is there a valid business case?  In some markets cost is king, but these usually have the high volume characteristics discussed, others have different drivers, such as obsolescence, performance, device size or IP protection. You have to have a good understanding of your goals.

    Many designs that are low volume are successful, because the right technology and approach is selected. I am deliberately not quoting figures here as this leads to misconceptions, each design will only succeed if the business case is solid.

    When looking at costs you basically have NRE and unit price. You can forget about tool and tester costs as these are capital expenditure and are not charged to one particular project, unless you were starting from scratch, (test time will be part of the unit price calculation). NRE breaks down into four areas, of which not all will be applicable to every design.

    NRE for design, NRE for IP licensing, NRE for masks and fabrication and NRE for any qualification exercise (e.g. Automotive AEC Q100)

    Design NRE is calculated on an internal rate over the estimated project. I have seen many complex calculations for this and some really quite simple. At the end of the day it will be the price for getting the job done, it will include any specialist expertise, tools or equipment required to get the job done, such as testing, digital, RF, etc. It will be based on a project plan. The questions you may want to ask, are, is this fixed price? and what contingency is in here. I would expect a risk assessment to be discussed here, as Jonathan rightly points out a slipping specification guarantees re-spins as does trying to break the laws of physics

    NRE for IP licensing you would think was straight forward, but the third party IP providers do not have a standard price list and again it is negotiated on a case by case basis. It can be any combination of a one off payment and royalties. IP from the chip designers will normally be used as a way of reducing the design time and risk and will normally be offered as part of the service.

    NRE for fabrication goes up dramatically as the geometry goes down. That said there are a lot of designs that are done on 350nm and 180nm. The costs on these are very reasonable. Some fabs offer MLM's which gets you away from the shared wafer and gets you many engineering samples. You can also hold wafers at various stages, so any small design changes can be processed quickly. This process can be more expensive than a shared wafer but is a lot more flexible and often proves more cost effective.

    NRE for qualification will depend on your target market. Basic ESD and latch up are standard; anything else will require planning for.

    The unit price will depend on size, yield, test time, programming, volume etc.

    So as Scot says, the real cost of a custom ASIC can be a lot more than is first touted, it can also be a lot less. So when I get asked the question, what will it cost? I ask what is it?

  52. Brad Albing
    June 24, 2013

    @Carl – an excellent response – that could have been a blog all by itself. Some good details there to help explain costs – and an especially good breakdown of the NRE costs.

    Hope you can write more like that.

  53. CameronRobertson
    September 19, 2018

    Those prices do seem pretty reasonable if you were to ask me. However, are they fully customizable according to your own specs that you get to define or are there guidelines that you need to stay close too making it non-flexy afterall? I guess different groups of people would have varying needs, thus one has to really set a goal and aim to reach it. Once you have made an upfront payment, you wouldn't be able to go back and that amount isn't worth a trial and error run.

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