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The right way to design today’s base station RF transceiver ICs

Back in the 90s and on into the mid-2000s, when I was heavily involved in telecom with Burr-Brown and TI at Lucent/Alcatel-Lucent and Nortel (When it existed), RF transceiver design for base stations evolved from a baseband design, then into an IF architecture and on to the quest of a totally-digital radio concept which is ongoing today.

When focus turned to the inefficient base station power amplifier (PA) in the transmitter, Digital Pre-distortion (DPD) and Envelope tracking (ET) came on the scene to help increase efficiency.

The DPD architecture typically used a high-speed RF Sampling Digital to Analog converter (DAC) to sample the RF transmit signal and feed it back through a Digital Signal Processor with a proprietary DPD algorithm, or a Graychip dedicated IC (Later acquired by TI) and then later architectures moved on to an FPGA incorporating all that was needed.

The industry was not able, in those years, to have an ideal architecture for the DPD function which would be to have the DPD function reside in the High-Speed RF Sampling DAC IC—-until now.

Analog Devices is announcing today a solution for Small Cell and Massive MIMO systems that will be needed for the full deployment of a viable 5G ecosystem. An IC evolution known as “Radioverse” by Analog Devices, started with the AD9371 in June 2016 and now this latest addition, the AD9375, is the first wideband transceiver with an integrated DPD architecture onboard.

The DPD function has evolved now from a two-transceiver/two receiver (2T/2R) design architecture to a 'Smart System Partition' residing right in the AD9375 with dual receiver, a sampling observation DAC and a dual transmit DAC with DPD all in one IC. giving a precious 600 mW power savings in small cell and Massive MIMO architectures where Size, Weight, and Power (SWaP) are essential. (Image courtesy of Analog Devices)

The DPD function has evolved now from a two-transceiver/two receiver (2T/2R) design architecture to a ‘Smart System Partition” residing right in the AD9375 with dual receiver, a sampling observation DAC and a dual transmit DAC with DPD all in one IC. giving a precious 600 mW power savings in small cell and Massive MIMO architectures where Size, Weight, and Power (SWaP) are essential. (Image courtesy of Analog Devices)

Existing FPGA solutions, which this IC is replacing, have DPD algorithms that are not efficient enough for this new generation evolution to 5G small cell and Massive MIMO designs in a heterogenous architecture. The FPGA solutions also do not scale with Massive MIMO antenna count, but the AD9375 indeed does.

I love this architecture because it is the way that DPD needed to be properly deployed. Power efficiency in these systems translates to dollar savings for the telecom service providers, especially in the coming 5G standard. DPD power is reduced as much as 90% over the FPGA solution; SERDES lanes are half of the FPGA solution, so complexity and cost is lower and time-to-market is faster.

Another important aspect of what Analog Devices has done is to ensure functionality with key power amplifier vendors with ready-to-go PA + DPD solutions, complete detailed reports with linearization performance before and after DPD, efficiency vs. frequency and output power graphs as well.

Massive MIMO will have a plethora of small antennas and will be deployed on masts, buildings and other structures. These solutions need to be as non-intrusive to landscape and those locations will need to have the structural support to hold 64 to 128 arrays of Transmit/Receive Massive MIMO antenna cells. Now that can be done with this new architecture.

Here is a 64Transmit/64Receive Massive MIMO architecture with a Power and Lane savings over traditional architectures. (Image courtesy of Analog Devices)

Here is a 64Transmit/64Receive Massive MIMO architecture with a Power and Lane savings over traditional architectures. (Image courtesy of Analog Devices)

What is so important in getting these designs to market quickly is a Small cell radio Reference Design with DPD which Analog Devices will be providing for the sub-6GHz space. As 5G evolves towards higher frequencies like mmWave and above-6GHz in the future, I am sure we will see more innovations from Analog Devices towards the needs in those areas as well.

The AD9375 reference design with DPD is a complete JESD204B-to-Antenna design that attaches to the baseband system. It has a 2x2 LTE 20 MHz, 250mW output power per antenna, Band 7 FDD with integrated DPD. The BOM is also re-configurable to other radio bands. The design includes a transceiver, Pas, LNAs, Filters, and Power solution. The power consumption is less than 10W.

The AD9375 reference design with DPD is a complete JESD204B-to-Antenna design that attaches to the baseband system. It has a 2×2 LTE 20 MHz, 250mW output power per antenna, Band 7 FDD with integrated DPD. The BOM is also re-configurable to other radio bands. The design includes a transceiver, Pas, LNAs, Filters, and Power solution. The power consumption is less than 10W.

For more information visit the Analog Devices website.

1 comment on “The right way to design today’s base station RF transceiver ICs

  1. ChristopherJames
    June 29, 2018

    There is always a start to everything that we perform and when it comes to a business, a proper plan needs to be put in place to kickstart just that start. If the eventual goal has been set but nothing has been done to put a start to the whole development, then the idea simply cannot be executed. It is a whole chain of events that need to be carefully coordinated. One wrong step could mean the entire plan could be sabotaged.

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