Way back in the day, analog/digital converters (ADCs) had simple, parallel interfaces, either TTL or high-level CMOS. Many of these converters could be clocked down to zero samples/second: once you initiated and they completed a conversion, the result stayed visible, since their parallel output register was static until the next conversion cycle. (Digital/analog converters–DACs–had similar, parallel-buffered inputs.) From personal experience, I found such static, full-width inpu eased some of the initial hardware/software debug steps, in those days of crude tools and non-seamless interfaces (so much glue logic!). You could manually check the converter's output with a logic analyzer, scope, or even a voltmeter in a crunch.
The large number of IC pins this interface needed was not a big problem in 8- and even 10-bit resolution world. But as converter resolution went to 12, 16, 18, and even more bits, the parallel path became part of a package-size and PCB real-estate problem, both for the converter and associated processor; while maintaining signal integrity (SI) was also tough. Some vendors went to serial groups of 8 bits, in a sort of serialized parallel-interface mode.
Of course, the better answer for today's dense circuitry is a high-speed serial interface, pumping bits out (or taking them in) as a single signal path, sometimes with an associated clock signal. Levels have also changed, going from high-level single-ended to low-voltage differential signaling (LVDS) in many cases. Assuming you can support the requisite serial clock rate, the saving in cost due to smaller die and package, as well as board real estate, is significant. Fewer signal lines also simplify PCB track routing and thus the SI challenge.
But even that I/O standard, although well established, faces challenges. The JEDEC serial interface standard (JESD204) was ratified in April of 2006, and is compatible with many FPGA high-speed interfaces. One vendor, Linear Technology Corp, has announced a 16-bit, 80 Msps ADC (LTC2274) which they say is the first to meet this two-wire, 8b/10b encoded standard. This serial interface, in conjunction with FPGAs, should result in smaller high-performance systems.
But nothing in this business is static. Already, I envision the system designer of an application with a very large number of high-speed channels, such as a specialized detector array in a physics experiment or an high-end MRI scanner, thinking something like this: “hmmm, maybe I can use a lot of these converters and FPGAs in parallel, and really get some serious channel count along with high throughput.” Then before you know it, we're back to where we were years ago, with large banks of parallel paths, except now clocking at much higher speeds. As they say, sometimes what old is new again.
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