Dallas—Texas Instruments says its SN74SSTE32882 is the industry's first fully integrated register and phase-locked loop (PLL) for DDR3 registered dual in-line memory modules (RDIMMs).
“The SN74SSTE32882 is the first device on the market enabling the future of cost- and power-efficient registered DIMMs for next generation servers and high-end PCs,” said Kent Novak, general manager of the high-speed communications group.
Touting reduced power consumption and board space, the single-chip device supports data rates of 800 to 1,066 mega-transfers per second (MT/s). Manufactured in the company's 130-nm process technology, the SN74SSTE32882 also integrates a high-performance, low-skew buffer with the register and low-jitter PLL. Integrating the PLL eliminates the need to tune the memory module, thus simplifying design and board layout to accelerate server and RDIMM manufacturers' market entry.
This 28-bit 1:2 configurable registered buffer is designed for 1.5-volt VDD operation. One SN74SSTE32882 per DIMM is required to drive up to 36 SDRAM loads. The edge-controlled circuit outputs meet SSTL_15 specifications and are optimized for terminated DIMM loads. To provide maximum flexibility and support industry-standard DIMM configurations, the clock and control outputs can be programmed for the appropriate drive.
The SN74SSTE32882 fully supports parity features as defined by the Joint Electron Device Engineering Council (JEDEC) to improve server system reliability. The SN74SSTE32882 also supports spread spectrum clocking (SSC) to reduce EMI.
The SN74SSTE32882, in a 176-pin BGA with 0.65 mm ball pitch in an 11-by-20 grit, is sampling now and will be in full production in 3Q 2007.
Texas Instruments , 1-800-477-8924, www.ti.com