The Intel® QuickPath Interconnect operates at extremely high frequencies, so it is essential that circuit designers understand the many factors that affect differential signal integrity. This multipart article provides an analysis of the Intel® QuickPath Interconnect (Intel QPI) system design, which involves creating models and performing simulations in either the time domain or the frequency domain, or both.
It introduces methods for analysis, model creation, and simulation in the Intel Quickpath Interconnect time domain. Many of the technical issues discussed here apply both to Intel® QuickPath Interconnect and many other serial-differential (e.g. PCI Express™) and even single-ended interface designs. (Note : this article is a follow-on to a previous two-part article, “Understanding Factors Affecting Intel QuickPath Interconnect Signal Integrity”, click here for Part 1 and here for Part 2.)
This follow-on article is presented in three parts, as pdf documents (no registration required):
- Part 1 , 12 pages, presents linear and time-invariant modeling, transmitter modeling, and modeling, click here.
- Part 2 , 7 pages, presents interconnect component modeling, PCB trace effects, and packages, sockets, connectors, and vias, click here.
- Part 3 , 7 pages, presents time-domain analysis, ISI and crosstalk, jitter, and characterization locations, and will be posted February 22.
This article is based on material found in the book Mastering High Performance Multiprocessor Signalling by Dave Coleman and Michael Mirmak (used with permission, all rights reserved by the publisher, Intel Press). To go to the Intel Press web site to learn more about this book, click here.
About the Authors
Dave Coleman is a Staff Platform Application Engineer at Intel with 22 years of electrical engineering experience. At Intel, he specializes in enabling and integration of customer Intel® QuickPath Interconnect designs in Intel Server platforms. Dave is the coauthor of the PCI Express™ Electrical Interconnect Design book.
Michael Mirmak is a Technical Marketing Engineer at Intel Corporation. He has been involved with signal integrity modeling and simulation since 1996, developing platform guidelines and models for both processor and chipset products, in desktop, mobile and server applications. He has also served as chair of the IBIS Open Forum since 2003.