Dynamic voltage drop or DVD in a chip power grid segment is in essence transient noise. It is a complex superposition of various noise components of a typical chip power grid that reduces available power supply differential. DVD is a key measure of chip power integrity, and requires careful inspection during chip design. It is a sign-off gating aspect of chip power delivery.

Measured at points of interest on the grid, DVD is distinct from static (IR Drop) voltage reduction. But this distinction blurs at times depending upon the analysis method adopted. A review of such methods is thus useful – both to comprehend DVD and to recognize its derivation at present.

It is perhaps best to begin at the beginning as I've done in Chapter 1 of Power Integrity Analysis and Management for Integrated Circuits. In that chapter, 'Power, Delivering Power, and Power Integrity,' I delve into fundamental constituents of supply noise, introducing the *3 R's of Interconnect* : Resistance, Reactance, and Resonance. Chapter 2 details the response of power delivery networks (PDN's) to load stimuli. A separation of transient (AC) and static (DC) noise becomes clear through such response. The analysis described therein captures circuit behavior in the TIME domain. Figure 1 displays an example.

**Figure 1**

**Time domain simulation of supply noise at the chip-pkg interface.**

But such capture as in Figure 1 are ** nodal ** simulations: supply voltage variation at a circuit node with respect to an ideal ground. A chip is a two dimensional surface. Voltage variations across its power grid are typically captured as shown in Figure 2.

**Figure 2**

**IR Drop snapshot on segments of a chip power grid (See Reference 1).**

With X and Y dimensions displaying the actual chip power grid, color shows voltage variation in the IR Drop snapshot of Figure 2. Note that spatial variation of noise provides useful information though time variance is absent. One sees the development of areas of greater current density and corresponding voltage reduction. Yet, such a snapshot captured hides many inadequacies as discussed in **Reference 1** . Given the computational complexity of such analysis on a ULSI chip, software tools reduce power grid segments to their base resistance, for example. Such reduction in IR Drop analyses loses at least two rigors of the *3R's of Interconnect* .

**Frequency Domain Analyses**

PDN's on printed circuit boards (PCB's) and chip packages are also analyzed in parallel in the FREQUENCY domain. Lumped approximations for PCB aspects, and impedance measurements, facilitate such analyses. Chapter 5 in **Reference 1** discusses this in detail and describes the *target impedance* design method often pursued. Through lumped abstractions for electrical behavior, one can also correlate frequency domain characteristics with time domain behavior. Figure 3 illustrates such correspondence.

Note that transient noise resulting from the excitation of PDN's by load spectral components at impedance peaks are called 'Droops.' The term 'Voltage Drop' is usually reserved for static reductions in voltage or to averaged noise levels.

Circuit-accurate responses and droops (1st, 2nd etc.) are in Figure 1. Figure 3 illustrates only the correspondence between time domain responses and frequency domain aspects.

**Figure 3**

**Hand-drawn sketch of frequency domain impedance variation and corresponding time domain voltage noise responses. See Reference 2.**

**Figure 4**

**Frequency domain design of a board PDN. See Reference 2.**

But frequency domain analysis abstracts electrical behavior, including *resistance, reactance,* and *resonance,* to a single aspect: **impedance** . It ignores vector phase relationships and surface noise wave propagation and interference. Besides, impedance measurements are made at a node, just as time-domain noise variance is measured at a circuit junction. Hence the applicability of this method to a surface, attached to distributed and varied electrical components, such as a chip power grid, is rather limited. And, as established in theory in Chapter 5 of **Reference 2** , the target impedance of a PDN is not a reliable indicator of maximum possible noise.

Nevertheless, frequency domain analyses continue to assist PCB and package design. Figure 4 illustrates a design procedure that attempts to meet a given impedance target. A combination of the frequency response of a chip model and the characteristics of the board PDN results in an impedance peak at ∼ 109 MHz. Observe the impedance characteristic of the chip: it is a simple capacitor-resistor model. Its impedance falls linearly on a log-log plot as frequency increases, flattening out to its effective series resistance at the end of the range. Further analysis in **Reference 2** shows that package inductance plays a large role in determining the combined impedance peak as seen at the board/chip interface. An extension of the same finding establishes that local, on-chip, power grid impedance thus depends upon inductance to on-chip decoupling capacitance.

**Bridging Time and Frequency Domain Analyses**

In **Reference 2** , we explored a method bridging traditional circuits-based time domain analyses with systems-level frequency domain analyses. It is conceptually simple: derive responses to individual spectral components of load in the frequency domain, transform these responses into the time domain, and superpose them for a complete response. But this procedure glosses over much information lost. For one, frequency domain analysis uses lumped approximations. Spatial and time/phase relationships between spectral components may not matter in lumped individualized responses. Abstraction in frequency domain analysis thus loses such significant information that matters in the time domain. And, lumped modeling isn't suited to varied and distributed circuit loads and capacitance connecting to a power grid surface.

**Figure 5**

**A DISTRIBUTED PDN model, chip/pkg/board grids and components. See Reference 1.**

It's important to ask why such analysis domain bridging may be useful. Chip design employs the time domain, while some circuits such as amplifiers and filters are verified in the frequency domain. Full-chip integration and PI analysis use time domain analyses. Though spatial IR Drop analysis employs the time domain, the very next electrical interface – the package and board – are analyzed in the frequency domain.

This disconnect in design and verification environments is great cause for concern. It is clear that package and board components have a dominant role to play in determining on-chip PI. Hence a holistic, seamless design (*see Slide 10 of the linked presentation* ) and verification environment for interconnect and PI is essential.

**PI-FP** is just such an analysis environment. While IR Drop provides spatial views, the absence of reactive and resonant aspects, and spatial noise wave propagation, renders it non-physical. IR Drop simulations **break the speed of light**, a fundamental law of physics. While frequency domain analyses include resistance, reactance, and resonance, they lose spatial time/phase relationships and cannot readily use time domain load currents available during chip design. Besides, FD analysis lumps system properties to impedance measurable at a junction. To derive true dynamic noise on a chip power grid, we need spatial + temporal + 3R's + dynamic aspects captured. In essence, the best capabilities of both TD and FD analyses combined. PI-FP provides such a spatiotemporal environment, and additionally provides true-physical representation of circuits, capacitance, and power pathways as distributed area components and grids. Figure 5 illustrates a typical PI-FP PDN model, and Figure 6 a simulation result snapshot of its noise **animation**.

**Figure 6**

**Spatiotemporal, dynamic chip power grid noise. See Reference 3.**

**Why Change from Time and Frequency Domain Analyses?**

I won't quote clichés such as “Change is the only constant.” I'd argued in the past (**Reference 4** ) that simulation complexity will explode in the nanoscale regime. And it has: PI verification simulations take *many hours to days* in ULSI designs today. And why is it still verification, a back-end task, when it has serious performance implications? Why is it not part of design and optimization?

A key point: we envisioned PI-FP as a front-end design optimization tool. As in Figure 7, we saw PI-FP entering into the chip design flow before routing. Given a projected severity of routing congestion, optimizing the allocation of metal between power grids and routing channels seemed to us a critical task. Besides, PI studies could revise block placements and decoupling capacitance inclusion, changing route vectors and constraints. A chip floorplan thus optimized through early PI analyses seemed to us the best path to a correct-by-design physical layout.

**Figure 7**

**PI-FP Methodology. See Reference 1**

We wrote in **Reference 4** that: “[Complex PI] *noise distribution cannot be predicted using a static analysis or dynamic IR drop tool as it is the result of complex interactions between edge timings, block placement, grid impedance and variable wave velocities (caused by variable capacitance per unit area in different parts of the chip). Again, this type of analysis is best done using tools that perform realistic simulations in minutes rather than hours or days. This makes it possible to complete the large simulation based experimental designs, covering the large parameter space (capacitance, width, space, placement etc.) required for this type of complex power grid design, within a reasonable timescale.* ”

Even more important is avoiding errors in analysis and inference arising from approximations. Peak IR Drop analysis calculates peak noise as peak current multiplied with grid resistance. I've shown that peak noise often does not correlate with peak currents in this Planet Analog blog Non-correlation of Peak Noise and Peak Current. Or, with noise estimated as *i⋅r* + *L⋅di/dt* , Dynamic IR Drop uses package inductance for 'L.' An egregious assumption, for di/dt on-chip, at an IP Block node, is different, often much higher, from *di/dt* at a package/chip junction. Besides, the local on-chip inductive effect relates to distance and interconnect to neighboring capacitance. Such local inductance varies all over the chip power grid.

One may also assume, from *L⋅di/dt* , that high frequency load components produce higher noise. And thus use spectral (FD) analysis of load waves to guide clocking in the time domain. But, as in a study of **Clocking and PI**, a sinusoidal load wave shape may not be the most desirable. Besides, exploration of low noise load current wave shapes may well be IP Block specific.

A frequency domain analysis environment, as illustrated in Figures 3 and 4, may show multiple impedance peaks below an impedance target for a PDN. This, as in **Reference 2** , is no guarantee of peak noise below the limit that defines the impedance target. Varied load excitation may stimulate the PDN at more than one impedance peak. Spatially adjacent load blocks may manifest noise waves that propagate and interfere constructively. The resulting noise waves can superpose and grow much greater than the limit set. Such waves are often called Rogue Waves, and manifest both in oceans and optical links. FD impedance targets met thus do not limit system noise.

A holistic, true-physical environment eliminates many approximations. True-physical accuracy also lends greater confidence in design choices and inferences. Would you instead settle for analysis environments with approximations and lumped component representations?

**Takeaways**

1) A **Spatiotemporal** analysis environment extends time and frequency domain capabilities. See **Reference 1**

2) Holistic models and analyses result from integrating key time and frequency domain aspects.

3) True-physical PI analysis can/should be a **front-end design** and optimization procedure. See **Reference 4** .

For more on **PI-FP**, or holistic PI analysis/experiments, please do not hesitate to contact us.

**References**

- Raj Nair and Donald Bennett, Anasim Corp. “Power Integrity Analysis and Management for Integrated Circuits,” Pearson Education – Prentice Hall, 2010.
- M. Hashimoto and Raj Nair, “Power Integrity for Nanoscale Integrated Systems,” McGraw Hill, 2014.
- Raj Nair, Anasim Corp. “IC Floorplanning and Power Integrity,” SOCcentral 2010.
- Raj Nair and Donald Bennett, Anasim Corp. “Beyond IR Drop: Dynamic Voltage Droops and Total Power Integrity,” March 2008.

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