As the Rolling Stones say, “Time is on my side” — especially with high-speed clocks and SYSREF on JESD204B. I regularly talk with system designers wrestling with timing for their JESD204B design. It seems to be a big challenge. Here’s what I’ve learned from my conversations so far.
For a subclass 1 JESD204B implementation, designers face the following challenges to achieve timing closures for sampling synchronization: PCB layout considerations, source synchronous clock and SYSREF generation to meet timing, SYSREF periodicity, and digital FIFO delays. Subclass 1 JESD204B implementations use the SYSREF signal as the starting point for JESD204B deterministic latency. A good source for SYSREF is a high precision clock or fan-out buffer.
So the first decision for the system designer is to decide how the device clock and SYSREF signal will be created and distributed throughout the system. Whenever possible, the device clock and SYSREF should be of the same swing level and offset. This will prevent inherent skew at the component input pin. Another “best-practices” approach is to make sure the update rate of the SYSREF event is determined as either a single event at start-up or as a recurring signal that may occur at any time synchronization is needed.
The next challenge is usually PCB layout. Taking the maximum clock and SYSREF signal skew into consideration, careful PCB layout is needed to meet setup and hold timing across boards, connectors, backplanes, and various components. Finally, digital FIFO design and signals traversing across multiple clock domains create inherent digital buffer skew within JESD204B transmitters and receivers that must be accounted for and removed in back-end data processing.
That’s the front-end of the implementation. A DAC or FPGA is usually added to the JESD204B receive path to buffer delays to the fastest lanes or fastest link to match that of the slowest, so that the framed data across converters lines up. The sample data on a JESD204B link is framed by an internal frame clock, which is then divided down further to form a multi-frame clock.
The multi-frame clocks on transmit and a receive devices will be the same frequency based on initial framing characters. But, they will not be phase aligned until a synchronous timing alignment signal, SYSRF for subclass 1, forces the phase of the multi-frame clocks to be locally aligned. Once this happens, the deterministic latency between two converter devices can be maintained — and you can sing like Mick Jagger because time is on your side!