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Time Is On My Side… Yes, It Is!

As the Rolling Stones say, “Time is on my side” — especially with high-speed clocks and SYSREF on JESD204B. I regularly talk with system designers wrestling with timing for their JESD204B design. It seems to be a big challenge. Here’s what I’ve learned from my conversations so far.

For a subclass 1 JESD204B implementation, designers face the following challenges to achieve timing closures for sampling synchronization: PCB layout considerations, source synchronous clock and SYSREF generation to meet timing, SYSREF periodicity, and digital FIFO delays. Subclass 1 JESD204B implementations use the SYSREF signal as the starting point for JESD204B deterministic latency. A good source for SYSREF is a high precision clock or fan-out buffer.

So the first decision for the system designer is to decide how the device clock and SYSREF signal will be created and distributed throughout the system. Whenever possible, the device clock and SYSREF should be of the same swing level and offset. This will prevent inherent skew at the component input pin. Another “best-practices” approach is to make sure the update rate of the SYSREF event is determined as either a single event at start-up or as a recurring signal that may occur at any time synchronization is needed.

The next challenge is usually PCB layout. Taking the maximum clock and SYSREF signal skew into consideration, careful PCB layout is needed to meet setup and hold timing across boards, connectors, backplanes, and various components. Finally, digital FIFO design and signals traversing across multiple clock domains create inherent digital buffer skew within JESD204B transmitters and receivers that must be accounted for and removed in back-end data processing.

That’s the front-end of the implementation. A DAC or FPGA is usually added to the JESD204B receive path to buffer delays to the fastest lanes or fastest link to match that of the slowest, so that the framed data across converters lines up. The sample data on a JESD204B link is framed by an internal frame clock, which is then divided down further to form a multi-frame clock.

The multi-frame clocks on transmit and a receive devices will be the same frequency based on initial framing characters. But, they will not be phase aligned until a synchronous timing alignment signal, SYSRF for subclass 1, forces the phase of the multi-frame clocks to be locally aligned. Once this happens, the deterministic latency between two converter devices can be maintained — and you can sing like Mick Jagger because time is on your side!

10 comments on “Time Is On My Side… Yes, It Is!

  1. RedDerek
    May 31, 2013

    Not too familiar with JESD204B, but I could add that if running parallel lines, another key would be to ensure the data lines are of the same length. Thus ensuring all data to arrive at the same time. This is a practice on many PC motherboards.

  2. eafpres
    May 31, 2013

    Speaking of clocks and timing, I just came across this article:

    NIST Scientists awarded Rank prize

    The award was for development of chip-scale atomic clocks back in 2004.  The article indicates some are commercialized now.  Here is one from Symmetricom:

    Symmetricom CSAC

    This part has a short-term accuracy of 5 parts in 10-12

  3. Brad Albing
    May 31, 2013

    @RedDerek – that trick with the PC board traces is where you need to start when dealing with these timing issues. Then you pursue some of the ideas that Mr. Beaver talks about. Important to keep in mind that if you are the analog design engineer on the project, you will need to help the digital guys deal with the subtleties involved here. They will likely be the victims of confused thinking.

  4. Brad Albing
    May 31, 2013

    @eafpres >>The award was for development of chip-scale atomic clocks back in 2004 . Hmm – 9 years ago. Wonder if the work for which they won is still relavant (not withstandin the fact that Symmetricom is still marketing product)….

    Still, that's prety good accuracy.

  5. eafpres
    May 31, 2013

    @Brad–at least the guys getting the award are still alive!

    If I'm not having another “episode” I estimate the drift at 150μs per year .

  6. SunitaT
    May 31, 2013

    Speaking of clocks and timing, I just came across this article: NIST Scientists awarded Rank prize


    @eafpres, thanks for sharing this info. Accurate  chip-scale atomic clock are very helpful in navigating locations where a global positioning system (GPS) doesn't work. I am curious to know if this technology is already commercialized ?

  7. SunitaT
    May 31, 2013

    but I could add that if running parallel lines, another key would be to ensure the data lines are of the same length.

    @RedDerek, true. Running parallel lines definitely helps us to make sure that data arrives at the same time. But we need to make sure that cross talk doesnt happen if two signals are running parallel. Shielding needs to be done to make sure that cross talk doesnt happen.

  8. eafpres
    May 31, 2013

    Hi Sunita–the only commercial one I'm aware of is the Symmetricom part:

    Symmetricom CSAC

    It might be of interest that Symmetricom is in the Smithsonian regarding this part:

    Smithsonian page CSAC

    The NIST experimental version is also on display:

    NIST Chip Scale Atomic Clock

  9. bjcoppa
    June 3, 2013

    Whether it be PCBs or chips themselves, foundries are collaborating more with design firms to improve their product design kits (PDK) since their main expertise lies more on the wafer process and integration side of manufacturing. It is a win-win for both sides and these companies do not directly compete and synergistic benefits can be derived. Mentor Graphics and TSMC are a good example.

  10. Brad Albing
    June 4, 2013

    @analoging >>foundries are collaborating more with design firms to improve their product design kits (PDK)…. Someone should write a blog that speaks specificially to that collaboration process, the benefits, etc. Any takers?

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