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Timing Solutions – for enterprise to core applications

Zarlink Semiconductor has announced a pair of timing chips that in combination delivers the industry's most complete feature set and best performance for SONET/SDH (Synchronous Optical Networks/Synchronous Digital Hierarchy) and PDH (Pleisiochronous Digital Hierarchy) systems.

The company's DPLLs (digital PLLs) and APLLs (analog PLLs) are targeted at line cards used in a broad range of equipment from the enterprise to the network core. The ZL&#8482 30106 DPLL has an unparalleled QC-3 jitter compliance margin and offers the industry's fullest feature set, including hitless reference switching, reference monitoring and holdover. When used in combination with the ZL30416 APLL, Zarlink's proprietary DPLL frequency synthesis technique minimizes low frequency phase noise, allowing designers to optimize the APLL bandwidth and achieve overall superior jitter performance and error-free transmission.

The ZL30416 APLL performs jitter attenuation and rate conversion for SONET/SDH equipment, and is specifically designed to meet the feature and performance requirements of line card applications from OC-3/STM-1 up to OC-192/STM-64 transmission rates. The chip generates ultra-low jitter output clocks that meet Telcordia GR-253-CORE jitter specifications up to and including OC-192 and is compliant with G.813 Option 1 and Option 2 jitter generation requirements up to and including STM-64.

Zarlink Semiconductor , 91944 Les Ulis Cedex A, France.
www.zarlink.com

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