Considerable effort is typically expended to optimize the layout of silicon semiconductor devices to minimize area. This strategy boosts the number of die per wafer, and hence, minimizes unit cost. CMOS image sensors are subject to different economics as each has to be paired with a lens train to realize a solid-state camera module. To achieve the smallest form factor camera module, the silicon layout must be compromised, but has the consequential benefits of decreasing assembly cost and improving product reliability by facilitating packaging innovation.
Solid State Image Sensors
Solid-state image sensors are finding application in an ever-widening variety of products. The largest market, by volume, is camera modules for mobile phones. More than two million cameras are made each day of the year purely for this application.
The vast majority of solid-state image sensors are based on complementary metal-oxide semiconductor (CMOS) technology as this provides a more integrated solution than such competing approaches as CCD (Charged-Coupled Device). A CMOS image sensor comprises a 2-D array of solar cells, which provide the optic-electric conversion function, with additional electronics blocks for picture, interface and power management.
Non-Optimized Silicon Design
Image sensors are perhaps unique among semiconductor devices in that the die layout is not driven by the need to obtain maximum wafer utilization. For normal semiconductors, die layouts are usually organized to achieve the maximum number of die per wafer, as this minimizes unit die fabrication costs. However, an image sensor is just one of the components required to make a camera module. Other key parts include a lens train, adjustable lens housing, infrared filter, substrate, and frequently passive components and decoupling capacitors. A breakdown of the relative costs of these parts for a typical 1.3M pixel camera module is illustrated in Figure 1. Because the cost of the optical parts exceeds those of the semiconductor, a compromise must be struck between the silicon layout and the optical design, with the driving forces being product cost and size.
First generation image sensors were generally fabricated following standard semiconductor rules. Optimizing die layout requires that the imaging area be located close to one corner of the die, so that the electronics blocks can be grouped together. To complete the camera module, a lens train needs to be centered over the imaging area (See Figure 2). Because the imaging area is located in one corner of the die, the area dimensions of the camera module have to be large to accommodate the protrusion of the optics outside of the die area. Now consider a modern image sensor where the die has been inefficiently designed from the point of view of silicon utilization, but where the imaging area is centered in the die (See Figure 3). All other factors being equal, the die is approximately 8 percent larger than in the previous case, but the lens train sits neatly over the die, resulting in an overall reduction in the size of the camera module by about 10 percent, by plan area.
Cost Reduction and Reliability Enhancement
A consequential benefit of distributing the electronics blocks around the active imaging area is that it forces the die bond pads to be distributed around the periphery of the die. This simple change was instrumental in rendering CMOS image sensors compatible with wafer-level packaging, which became a commercial reality in 2000.
Wafer-level packaging of semiconductors is an economically attractive proposition because the process costs are shared among the good die on the wafer. With a few thousand die on a 200mm diameter wafer, the wafer-level package cost is just cents per die. The dimensions of a wafer-level package, in plan, are dictated by the size of the die. As completed packages are diced directly from the wafer, the chip and the package dimensions are one and the same. This attribute is unique among semiconductor packaging solutions and hence wafer-level packages are sometimes also referred to as “chip-scale packages.”
The optically active area of solid state images sensors is vulnerable to mechanical and environmental damage, not least because this surface is covered with delicate optical components including a color filter and micro lens array. Wafer-level packages for image sensors provide protection to theses structures by bonding a glass wafer to the front face of the device wafer. However, the bond pads are then rendered inaccessible, denying connection by the traditional method of wire bonding.
Theoretically, it should be possible to make connection to the bond pads by drilling through the thickness of the silicon. However, despite many years of endeavour through silicon via (TSV) technology, as it is called, has failed to be widely adopted because of the need for specialist capital equipment to fabricate the via and the reliability of TSV interconnects has not been satisfactorily solved at a competitive cost.
The only wafer-level package solution adopted by industry in high volume is edge contacts. As their name suggests, contact is made to the edge of the bond pads and a wiring trace provides a conductive pathway to a ball grid array (BGA) on the rear face of the package. This style of contact has proved to be extremely robust and reliable, while the BGA renders the packaged imager compatible with pick and place reflow assembly, like all the other components of the cell phone. The compatibility with lead-free surface mount assembly eliminates the need for a flexible circuit and connector to integrate an imager in a cell phone. Connector failure is the principal cause of field returns for camera phones. In 2006, more than 225 million image sensors were housed in edge contact wafer level packages and it is forecast that by 2011 more than 50 percent of all CMOS imagers will be packaged in this manner [Prismark 2007].
Edge contacts have a minor drawback in that die on the wafer have to be spaced slightly wider apart than usual to provide access to create the structures. Consequently, the maximum number of die that can fit on a wafer is decreased, slightly increasing unit cost. This issue is circumvented in the latest generation of wafer-level package for image sensors which use a via-through-pad interconnect. An example of this is shown in Figure 4. The interconnect is still an edge contact, but it is radially symmetric within the area of the bond pad. Not only does this permit the dicing lanes to be as narrow as the silicon design rules allow, but it removes many restrictions on the bond pad size, pitch and location, making this style of wafer-level package directly compatible with the majority of existing CMOS imagers.
Innovation in materials and process has decreased the packaged imager thickness to approximately 500μm, making it imminently suitable for electronics products where the current fashion is for extreme thinness. These benefits translate directly in to reduced product cost making wafer-level packaging with via-through-pad interconnects a key enabler to a “Holy Grail” of the cell phone industry, namely the $1 VGA camera module.
Prismark, 2007. Prismark Partners LLC, November 2007
About the Author
Giles Humpston , Ph.D., serves as Director, Research and Development of Tessera. Dr. Humpston has spent his entire professional career working in the field of semiconductor packaging, initially for military applications and more recently for high volume consumer products. He is a metallurgist by profession and has a doctorate in alloy phase equilibria. Dr. Humpston is a cited inventor on more than 75 patents and has co-authored several text books on metallic joining processes. His work and technical publications have been recognized by five international awards. Dr. Humpston's current interests are packaging of solid-state camera modules and product miniaturization through wafer level technologies. He can be reached at: .
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