Power management ICs already contain power MOSFETs as integrated elements. This includes switching regulators with integrated FETs, of course, but also includes the driver ICs, which themselves contain power FETs. So conceptually, a discussion of the integration of power elements onto a chip may not seem like news. However, as higher-power devices are added to highly integrated mixed-signal ICs, getting rid of the heat becomes a significant issue.
The issue of power and RF — with its own peculiar needs for packaging — has been touched on here before (see related posts, below). Anything that can shrink the package size will shorten the heat path and reduce parasitic reactances — a double bonus.
First, a quick look at the packaging of power devices and how they've evolved. Every time power transistor technology improves, the package gets in the way. In the 1970s the most popular power package was the TO-3, an all-steel, diamond-shaped, through-hole monster by today's standards. When the power MOSFET came along late in the decade, the TO-3 proved too large and had too much inductance for the high frequencies and power densities now enabled.
Through the years, power packages have continued to evolve in response to improvements in transistor technology. The TO-220 was one such change. The surface mount version of that package was the next. Even with improvements, packaging can still cause problems and be the bottleneck in systems.
We are seeing more use of the GaN enhancement mode transistor. From the packaging perspective, these devices are nice to use. The switch is isolated from the base silicon material, making it possible to place multiple devices on the same Si chip. This not only eliminates parasitics but allows for higher integration onto the chip — other functionality plus passive components.
Packages only detract from a device's performance, and they do it in five ways:
- Packages add cost — for a commercial power MOSFET the package cost is about half the total cost.
- Packages add size — as FETs get smaller the package limits gains in PCB space and increases the length of circuit interconnects.
- Packages add thermal resistance — as FETs get smaller the package becomes more of a thermal bottleneck.
- Packages add resistance — as FETs get closer to zero on-resistance the package resistance from leads and wire bonds stands out more and more.
- Packages add inductance — as FETs get faster the package inductance starts to dominate circuit performance.
While developing the material and process technology to manufacture enhancement mode GaN-on-silicon transistors at EPC (eGaN FETs), we searched for a package that could keep up with our devices while maintaining a reasonable cost. Unfortunately, we couldn't find one.
As a result, we decided to eliminate the package altogether — no added resistance, inductance, size, or cost. eGaN FETs are encased in glass and plastic during the wafer fabrication process, so there wasn't even a need for any extra environmental protection.
By applying standard solder bump technology to the eGaN FETs while still in wafer form, a Land Grid Array (LGA) format could easily be achieved at minimal cost. Standard assembly techniques apply, and efficient thermal conduction can occur either through the device to the PCB, or through both the bottom and top of the device, using a heatsink for higher power density. Since the transistor is mounted directly to the PCB, there is no added resistance. To show the large benefit this configuration has on the thermal resistance let's first look at a conventional packaging configuration with a transistor in a molded epoxy package:
The thermal resistance of this system from the device to the ambient (RθJA ) is given by the simple equation:
- RθJA = RθJC + RθJTIM + RθJHA
In this formula RθJC is the thermal resistance from the active part of the transistor, RθJTIM is the thermal resistance of the thermal interface material, and RθJHA is the thermal resistance of the heatsink to the ambient air.
Now, compare this with the LGA package. It has multiple paths for heat to get from the device to the ambient as shown in Figure 3:
The LGA package with a heatsink has two parallel paths to ambient: The first is through the back of the device and the heatsink, and the second is through the front of the device and into the PCB. The formula describing the overall resistance from the transistor to ambient is as follows:
Here we have added in parallel the thermal resistance from the junction of the transistor to the PCB (RθJB ) and the thermal resistance from the PCB to ambient (RθJA ). By adding the additional parallel path we are able to pull heat more efficiently from both top and bottom without any interstitial packaging to add to the series path.
Checking back on the five “detractors” above, we have minimized the first four: no added cost, size, thermal, or electrical resistance. What about inductance?
Given that these FETs are faster than conventional FETs in silicon, the inductances are more important than ever. In Figure 4 we show the power losses only due to package inductance in a 1 MHz point of load (PoL) converter. MOSFET packages such as SO-8, LFPAK, or DirectFET have enough parasitic inductance to cause more power losses than the silicon device inside. This is caused by the package inductance slowing down the switching transition. In contrast, the eGaN FET in an LGA format has only 18 percent added power losses due to the inductance of the package.
Designers will always want transistors to be smaller, cheaper, and more thermally and electrically efficient. Combining that with the need for higher levels of integration points to the need for a packageless technology. It provides the building blocks for today's integration needs as well as tomorrow's evolutionary needs. For the new generation of power transistors based on gallium nitride, no package can keep pace… and that's why there's no package for eGaN FETs.
Have you used any packageless power transistors? Were there any complications?