Transistor Packaging: A Thing of the Past?

Power management ICs already contain power MOSFETs as integrated elements. This includes switching regulators with integrated FETs, of course, but also includes the driver ICs, which themselves contain power FETs. So conceptually, a discussion of the integration of power elements onto a chip may not seem like news. However, as higher-power devices are added to highly integrated mixed-signal ICs, getting rid of the heat becomes a significant issue.

The issue of power and RF — with its own peculiar needs for packaging — has been touched on here before (see related posts, below). Anything that can shrink the package size will shorten the heat path and reduce parasitic reactances — a double bonus.

First, a quick look at the packaging of power devices and how they've evolved. Every time power transistor technology improves, the package gets in the way. In the 1970s the most popular power package was the TO-3, an all-steel, diamond-shaped, through-hole monster by today's standards. When the power MOSFET came along late in the decade, the TO-3 proved too large and had too much inductance for the high frequencies and power densities now enabled.

Through the years, power packages have continued to evolve in response to improvements in transistor technology. The TO-220 was one such change. The surface mount version of that package was the next. Even with improvements, packaging can still cause problems and be the bottleneck in systems.

We are seeing more use of the GaN enhancement mode transistor. From the packaging perspective, these devices are nice to use. The switch is isolated from the base silicon material, making it possible to place multiple devices on the same Si chip. This not only eliminates parasitics but allows for higher integration onto the chip — other functionality plus passive components.

Packages only detract from a device's performance, and they do it in five ways:

  1. Packages add cost — for a commercial power MOSFET the package cost is about half the total cost.
  2. Packages add size — as FETs get smaller the package limits gains in PCB space and increases the length of circuit interconnects.
  3. Packages add thermal resistance — as FETs get smaller the package becomes more of a thermal bottleneck.
  4. Packages add resistance — as FETs get closer to zero on-resistance the package resistance from leads and wire bonds stands out more and more.
  5. Packages add inductance — as FETs get faster the package inductance starts to dominate circuit performance.

While developing the material and process technology to manufacture enhancement mode GaN-on-silicon transistors at EPC (eGaN FETs), we searched for a package that could keep up with our devices while maintaining a reasonable cost. Unfortunately, we couldn't find one.

As a result, we decided to eliminate the package altogether — no added resistance, inductance, size, or cost. eGaN FETs are encased in glass and plastic during the wafer fabrication process, so there wasn't even a need for any extra environmental protection.

It worked!

Figure 1

An eGaN FET in a Land Grid Array (LGA) format. This device is 4.6mm x 1.7mm and can conduct 33A DC.

An eGaN FET in a Land Grid Array (LGA) format. This device is 4.6mm x 1.7mm and can conduct 33A DC.

By applying standard solder bump technology to the eGaN FETs while still in wafer form, a Land Grid Array (LGA) format could easily be achieved at minimal cost. Standard assembly techniques apply, and efficient thermal conduction can occur either through the device to the PCB, or through both the bottom and top of the device, using a heatsink for higher power density. Since the transistor is mounted directly to the PCB, there is no added resistance. To show the large benefit this configuration has on the thermal resistance let's first look at a conventional packaging configuration with a transistor in a molded epoxy package:

Figure 2

Transistor in an epoxy package mounted on a heatsink. The thermal resistance model is on the right.

Transistor in an epoxy package mounted on a heatsink. The thermal resistance model is on the right.

The thermal resistance of this system from the device to the ambient (RθJA ) is given by the simple equation:

    RθJA = RθJC + RθJTIM + RθJHA

In this formula RθJC is the thermal resistance from the active part of the transistor, RθJTIM is the thermal resistance of the thermal interface material, and RθJHA is the thermal resistance of the heatsink to the ambient air.

Now, compare this with the LGA package. It has multiple paths for heat to get from the device to the ambient as shown in Figure 3:

Figure 3

eGaN FET in an LGA format mounted on PCB with a heatsink on the back of the transistor. The thermal resistance model is on the right.

eGaN FET in an LGA format mounted on PCB with a heatsink on the back of the transistor. The thermal resistance model is on the right.

The LGA package with a heatsink has two parallel paths to ambient: The first is through the back of the device and the heatsink, and the second is through the front of the device and into the PCB. The formula describing the overall resistance from the transistor to ambient is as follows:

Here we have added in parallel the thermal resistance from the junction of the transistor to the PCB (RθJB ) and the thermal resistance from the PCB to ambient (RθJA ). By adding the additional parallel path we are able to pull heat more efficiently from both top and bottom without any interstitial packaging to add to the series path.

Checking back on the five “detractors” above, we have minimized the first four: no added cost, size, thermal, or electrical resistance. What about inductance?

Given that these FETs are faster than conventional FETs in silicon, the inductances are more important than ever. In Figure 4 we show the power losses only due to package inductance in a 1 MHz point of load (PoL) converter. MOSFET packages such as SO-8, LFPAK, or DirectFET have enough parasitic inductance to cause more power losses than the silicon device inside. This is caused by the package inductance slowing down the switching transition. In contrast, the eGaN FET in an LGA format has only 18 percent added power losses due to the inductance of the package.

Figure 4

Power losses caused by package inductance are a significant fraction of total losses in traditional power MOSFET packages. eGaN FETs in an LGA format have less than 18% added losses due to the package.

Power losses caused by package inductance are a significant fraction of total losses in traditional power MOSFET packages. eGaN FETs in an LGA format have less than 18% added losses due to the package.

Designers will always want transistors to be smaller, cheaper, and more thermally and electrically efficient. Combining that with the need for higher levels of integration points to the need for a packageless technology. It provides the building blocks for today's integration needs as well as tomorrow's evolutionary needs. For the new generation of power transistors based on gallium nitride, no package can keep pace… and that's why there's no package for eGaN FETs.

Have you used any packageless power transistors? Were there any complications?

Related posts:

18 comments on “Transistor Packaging: A Thing of the Past?

  1. goafrit2
    August 9, 2013

    >> Have you used any packageless power transistors

    Yes, I have made wafer level chip scale package for inertial sensors. They are done differentially since there is a mechanical beam for the gyroscope/ XLs but the fundamental strategy is to do away with packaging and save about 70% of the cost of the chip.

  2. eafpres
    August 9, 2013

    @Alex–this type of packaging and attachment seems to dovetail very well with using thermally enhanced PCBs.  There are a few vendors of the pre-preg and clad boards.  Have you seen this combined with the bare/upside down packaging concepts?

  3. RedDerek
    August 10, 2013

    @Alex – the other big development since those old TO-3 is the transistor technology. For MOSFETs, it went from a planar to vertical. Then the cell density has been increased – getting more MOSFETs in the same area. And finally, getting rid of bond wires. One can now get a 30 Vds MOSFET with resistances down to 0.5 mOhm. This would be a vertical MOSFET, with high cell density and using a source clip instead of bond wires (drain is still the mounting side and the gate could still be bond wired).

    So moving to a bumped die was the next level to cut any addional package parasitics (inductance and resistance).

    The GaN MOSFETs from Epcos and others incorporate additional technology that actually reduces the gate capacitance and sets the Cgs and Cgd in the right ratio to help minimize shoot-through conditions as a synchronous FET in a buck converter application.

  4. eGaN FET
    August 10, 2013

    @eafpres – I haven't seen any customers use thermally enhanced PCBs with our eGaN FETs.  It sounds like a good match.  What kinds of improvements have you seen with these PCBs?

  5. eGaN FET
    August 10, 2013

    @RedDerek – Your point about the capacitance is a very good one.  The miller ratio Cgd/Cgs  needs to be very low or the high dv/dt experienced during switching can turn the device back on.  We worked with TI on the LM5113 driver IC to make certain the pull-down resistance was very low (less than 0.5 ohm) for just this reason.  

    As long as the internal gate resistance and the common source inductance are low enough, the external gate drive can handle the dv/dt.  As we get faster devices, this capacitance and inductance becomes even more critical.

  6. RedDerek
    August 10, 2013

    Lowering the driver resistance is another method. I spent several years at Vishay as they were improving the Miller capacitance ratio. In fact, all the focus was on the N-channel MOSFETs that I started a push for the P-channels. I wrote a technical paper on this subject when Vishay finally produced the part. I left and the push seemed to have waned. Applications in small devices is ideal for the product. A link to my paper is

  7. eafpres
    August 10, 2013

    “What kinds of improvements have you seen with these PCBs”

    Sometimes it isn't practical to stick a heat sink on top of a package.  If you can design for it, the PCB can help you a lot.  For instance, regular FR4 has a thermal conductivity of about 1.7 W/mK. A product from a former employer of mine, Laird, is called Tlam and the dielectric has a thermal conductivity of 3 W/mK.  There are other suppliers as well.

    If you can add in a layer of aluminum as a heat spreader, that configuration has worked in small base stations where the RF chipset gets hot.  Doubling the TC of the board and adding a heat spreader (sometimes that is then thermally connected to the chassis) makes a big difference.

    In portable devices, where I imagine your products might be used, it is even harder, and there the enhanced TC can reduce hot spots in the crowded board layout.

  8. Davidled
    August 10, 2013

    I think that this chart is given based on math equation. If it is right, how do we validate this equation? Well, we might need to get the tool in order to measure power loss in terms of package and die. If different materials are used in the same package and die structure, heat dissipation might be variants. I do not sure small package is always providing the best solution in case of high power MOSFET. 


  9. eGaN FET
    August 11, 2013

    @Daej– We have done a lot of work validating thermal models.  One example is in the article on envelope tracking at


    We also have thermal models for all our eGaN FETs at


    It is tricky to exactly model thermal performance.  There are many variables that are hard to quanitfy with any precision including the thermal conductivity of the thermal interface materials and the thermal coupling of components mounted near each other on the PCB.  We try to validate our models in three ways: (1) we carefully calibrate device Rdson vs temperature in an oven, and then use this characteristic to infer the temperature at which the device is operating; (2) we use thermocouples monted very close to the device; (3) we use infrared cameras to see the device temperature.  

    eGaN FETs in an LGA format can be the most efficient package ever because there isn't anything added to the thermal path on either the front or the back.

  10. Netcrawl
    August 11, 2013

    @RedDerek they're getting smaller and more sophiscated these days, as electronic gadgets such smartphones get smaller, thinner and more sophisticated, more and more compact component are required.

    But its not an easy job for tech people, some serious problems, problems related to internal element miniaturization, package process accuracy and many more. But company like ROHM has managed to nail the problem by rolling out a much smaller transistor package optimized for compact and thin devices, packed with some key features like reduced MOSFET ON resistance.  



  11. Netcrawl
    August 11, 2013

    Good point! I believe MOSFET performance has improved over the last couple of years. The problem here is the lack of high performance packaging. This has become a major limiting factor. This help the develoment of such innovative solution like the DirectFET and PolarPAK. 


  12. Davidled
    August 11, 2013

    When accessing web page below,,

    many device models are presented. Unless missing anything, there is no any data comparison that Output of Thermal model should be almost the same as that of actual data from actual experiment before using model to present the data chart. Secondly, model might be updated over the course of time. Model might be a set of many variables including for example, heat sink size, material and location.


  13. eGaN FET
    August 11, 2013

    @Daej–There is a sample calculation in the application note at:, but you are right, there are many variables that are not in any model.

    The models on our web site were verified experimentally.  Here is the link to the paper describing the work:

  14. SunitaT
    August 20, 2013

    As miniaturization drives higher current densities in a wide range of electronic systems, designers are more aware than ever of the importance of thermally efficient packages for power semiconductor components. Vishay Siliconix package innovations addressing these demands include PolarPaK, with dual top and bottom cooling, and several versions of PowerPaK, each of which offers much better thermal performance than the standard package types with the same or similar footprint dimensions.

  15. eGaN FET
    August 20, 2013

    @SunitaT.  PolarPak is a good package for a vertical MOSFET.  The advantage of the eGaN FET in an LGA format is that there are no package interfaces to add thermal reistance along the way.  This makes a significant difference in dual-sided cooling.  The other advantage with the eGaN FET in an LGA format is that the sidewalls can radiate heat.  The sidewall area of an eGaN FET is almost the same as the total area of the die.  If you use a thermal interface material between the heatsink and the eGaN FET's silicon back surface, the spill-over to the sides of the transistor provide significant additional cooling which is not so much the situation with a conventional epoxy package.

  16. Brad_Albing
    August 26, 2013

    @Netcrawl – I wonder if (in the case of that smaller package) ROHM has made an important tradeoff. Usually, it's the breakdown voltage.

  17. Hughston
    September 18, 2013

    I've never heard of an aluminum layer as a heat spreader.  One of my friends told me he used 2 oz copper layers to spread the heat for base station transmitters. That's what I have always done.

  18. eafpres
    September 18, 2013

    Here are a couple of references on using Aluminum as the metal layer in a metal clad thermally enhanced PCB:

    Bergquist T-Clad

    Journal of HKPCA

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