SAN JOSE, Calif. — Seeking to accelerate the product development process, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is rolling out a one-two punch in the arena: It has unveiled a mixed-signal/RF design kit as well as a foundry-specific integrated sign-off flow.
TSMC's bigger announcement appears to be the so-called Integrated Sign-Off Flow, which is a turnkey EDA flow. The flow consists of specific and pre-qualified EDA and IP tools from multiple vendors, which are selected by the foundry giant. Customers must still buy the EDA tools from the third-party vendors. But because the flow has been qualified and tuned for TSMC's fabs, chip makers can bring a product to the market more rapidly by following the pre-defined and strict guidelines in the process.
The initial flow from TSMC (Hsinchu, Taiwan) is available for 65-nm designs. The new flow shortens the design cycle and improves tape-out quality, said Tom Quan, deputy director of design services marketing at TSMC.
''It's an executable flow,'' Quan said. ''We know there are a lot of people struggling with their own flows. We can help them.''
For years, the silicon foundry giant and its rivals have offered a design reference flow, which consists of various third-party EDA, DFM, IP and other tools. The flow provides a suggested guideline or path to enable a particular design.
In this model, chip makers must continue to evaluate and buy a complex raft of EDA, DFM and IP tools. This reference flow model works, but chip designs continue to get more complex and expensive.
To help customers, TSMC is taking another approach. Its Integrated Sign-Off Flow is a complete RTL-to-GDSII chip implementation flow. It consists of the exact and process-specific items, including pre-qualified libraries, IP and selected EDA tools.
There are some advantages in going this route. This is especially true for chip makers with lack of resources in their CAD departments. In its new flow, TSMC selects the EDA tools, as opposed to the chip maker itself. This in turn saves time and money. ''It takes an enormous amount of time to evaluate the tools,'' Quan said.
The disadvantage is a chip maker is tied to specific tools or design methodologies. The flow consists of several different pieces. Synopsys Inc. provides the place and route tools. Synopsys and Cadence Design Systems Inc. provide the signoff timing analysis (STA) tools. Apache Design Solutions Inc. provides the electro-migration (EM) and related tools. Mentor Graphics Corp. and Cadence provide the DFM products. And Azuro Inc. supports the clock-tree products.
The flow is not for all chip makers. ''Large fabless companies are early adopters,'' Quan said. ''They have their own flows.''
On the other hand, some large chip makers could also go the ''sign-off flow'' route. Quan added the flow could also be geared for a ''second wave'' of customers, many of which are still devising new 65-nm designs.
The timing could be ripe for such an offering. Amid a major downturn, the silicon foundry industry is expected to see a big and welcomed rally in the second quarter–and perhaps beyond.
Right now, major foundry vendors–Chartered, TSMC, SMIC and UMC–are all seeing a rebound after a huge drop in orders. The surge could be a replenishment cycle in the channels–or a real upturn–or a combination or both. More likely, it's somewhere in the middle.
Meanwhile, the TSMC 65-nm Integrated Sign-Off Flow is available now in limited release and at no charge to selective customers during Q2 2009. General release to other customers is targeted for Q3 2009.
In a separate announcement, TSMC and EDA partner Cadence have unveiled a mixed-signal/radio-frequency reference design kit, dubbed the MS/RF RDK. Geared for 65-nm designs, the kit aims to accelerate analog, mixed-signal and RF designs in the marketplace.
With the move, TSMC now appears to be throwing its weight behind two camps–Cadence and a rival technology. Last year, silicon foundry giant TSMC joined the Interoperable PDK Libraries industry alliance. The IPL group, which includes Magma, Mentor, Synopsys and other tool and intellectual-property vendors, is pushing for a standard foundry process design kit (PDK).
Today's analog-oriented PDKs are proprietary and incompatible. The IPL-backed version is said to support analog layout tools from all vendors over a common database, and to interoperate with Cadence's proprietary analog environment. But some view the IPL-backed flow as a competitive threat to Cadence's analog EDA tool suite, dubbed Virtuoso.
Quan said TSMC is still working with the IPL. In fact, it is supporting both camps to capitalize on the emerging analog and RF designs taking place at the 90- and 65-nm nodes.
TSMC and Cadence have already rolled out its first IP in the kit. The reference design in the RDK is a fractional-N phase locked loop (PLL) developed in TSMC's 65-nm RF process technology.
The RDK also includes the following pieces: a video tutorial and step-by-step design manual; the complete PLL reference design database with schematics, layouts, and simulation test benches; a design flow and methodology introduction; silicon test reports, release notes specifying design tool and version requirements and a TSMC 65-nm process design kit (PDK).
The TSMC 65-nm RDK is available now in limited release and at no charge to selective customers during Q2 2009. General release to other customers is targeted for Q3 2009.