Clock jitter is a parameter which affects system performance and can degrade otherwise superior component specifications. This article is a basic explanation of clock jitter and some of its effects, especially with respect to a phase lock loop (PLL).
At a very fundamental level, jitter is defined as the variation of a signal (in this case a clock output) from its ideal position in time, Figure 1 .
Figure 1.Basic definition of jitter aspects
In an IC, a PLL (frequency synthesizer) is typically used to generate the clocks.
Jitter in clocks has two different components which arise due to various sources.
(a) Random jitter (Rj). Rj arises due to thermal noise inherent in the system and exhibits a etermin distribution. Since Rj is unbounded it is characterized by its rms value. In a PLL, the low frequency RJ typically comes from the reference clock and Charge pump whereas the high frequency jitter is more a manifestation of the VCO thermal noise.
(b) Determinstic jitter (Dj). Dj arises due to eterministic components. Examples include: PLL reference freedthrough, Power supply noise etc. Unlike data, there is no Intersymbol interference (ISI) term. Dj is bounded and specified as a peak number
This deviation from its ideal position can negatively impact data transmission between two clocked elements on-chip as well as off-chip. Example of on-chip systems includes timing violations between two flip flops.
Example of off-chip systems include a Serdes I/O (serializer/deserializer) link where data is sent over long traces of FR4 PC-board substrate. Excessive high-frequency jitter on the clock used for transmitting the data can cause eye closure and excessive bit errors (bit error rate, or BER). In either case different types of clock jitter cause the errors mentioned above.Hence it is critical to understand what type of jitter is important for ones application and how to measure/analyze them.
Jitter Measurements–time and frequency interplay
Jitter can be measured in two different ways: in the time domain and in the frequency domain.
Time-domain measurement is implemented using a low-noise-floor, real-time oscilloscope. Such a scope samples the clock and looks at the deviation of the zero crossing from an ideal clock. (Note, since no reference clock is input to the scope, the ideal clock is actually a derived clock and is an average of the time period of the jittery clock over a large number of clock cycles).
The time domain deviations can be post-processed to derive other types of jitter. Fortunately most advanced scopes include a jitter package which makes the computation much easier.
Frequency-domain measurement typically uses a spectrum analyzer. A spectrum analyzer mixes the input jittery clock with a “clean” reference clock, and then displays the shifted spectrum of the signal (after some filtering to get rid of harmonics and other artifacts). While an ideal signal will just have one tone, a real signal will have skirts around it (due to Rj) and possibly low-amplitude tones or spurs (due to Dj), Figure 2 .
Figure 2: Frequency-domain measurement of a signal showing jitter-caused spurs
This is an exciting field with new instruments coming to market, such as signal source analyzer, which can measure open-loop responses as well.
An astute reader might wonder why bother about frequency-domain measurement when clocks are just used for timing elements. There are two main reasons for it:
(a) Certain applications actually specify their compliance in frequency domain. One major application is RF: GSM, WiFi and similar. For example, GSM requires the phase noise and spur level to be lower than -128 dB/Hz and -68 dBc in the range of 600 kHz to 1.6 MHz offset.
(b) Instruments used for frequency-domain phase noise analysis are typically more accurate than time-domain ones, especially in the region of high phase noise. Scopes suffer from timebase jitter as well as drift if it is necessary to take a larger sample size. (An excellent reference is Reference 1 ). A spectrum analyzer uses a very-low-noise oscillator to mix with the input data. A noise floor as low as -170 dB/Hz at larger offset frequency is not uncommon.
It is possible to convert between time and frequency domain. Integrating the phase noise over a frequency range gives total rms phase jitter (with a normalization factor). A valuable byproduct of this duality is the possibility of using spectrum analyzer to accurately measure jitter in the frequency domain, and then to convert into a time domain number, rather than using a higher noise-floor instrument such as a scope.
Jphase is the deviation of VCO output edges from ideal placement in time (Reference 2) :
Jperiod is the deviation of VCO period from ideal period. It is the derivative of the Jphase in time. This manifests itself as a sinc() function, (Reference 2) :
Where Fvco is the frequency of oscillation
And S(f) = 2L(f) is the dual-sideband phase noise
The integration period varies from standard to standard. For instance, PCIe specifies a lower limit of 1.5 MHz. The upper limit can be taken as half of reference frequency to make sure there is no aliasing effect.
Converting the spectrum into a Jphase rms ps number can be cumbersome since the phase noise has different regions (1/f3, 1/f2. 1/f etc) necessitating numerical integration in small increments. In addition, correction factors to take into account resolution bandwidth (RBW) need to be added in. Fortunately, newer instruments take the complexity out of the equation and spit out the correct ps rms number.
Unfortunately, there is no such package for Jperiod. Therefore, Jperiod typically involves post-processing the spectrum analyzer data with a sinc() function.
Now that we have a good understanding of measuring jitter, we need to find out which type of jitter is important for which application
a) In digital on-chip systems, it is the period jitter that is important. What we are most concerned about is whether the data delay from one flip-flop to the receiving flip-flop can tolerate a clock time period made lower by jitter. Therefore, in this case only high-frequency jitter (ie jitter which changes from within one clock period) is important. MTBF, RJ multiplication, and random period jitter are much less than rms jitter (which is integrated over the whole spectrum of phase noise). So if one considers just a PLL datasheet, quoting rms jitter it will likely be misleading and erroneous.
b) In communication systems (off-chip) the data is typically sent over long distances of FR4 traces. At the receiving end, a clock data recovery (CDR) circuit recovers the clock from the data and re-generates the data. In such a system, the untracked jitter between derived clock and received data is more important, and can span several cycles of clock. Unlike the on-chip digital systems.
c) RF systems depend upon the rejection of close-by interfering signals from the main signal path. The interfering signal gets mixed with the “skirts” from the oscillator. In such a case, the phase noise of the PLL is the critical parameter.
In some other types of communication systems (off-chip) the clock is sent with the data. In a way, they lie between (a) and (b) systems mentioned above. For the same BER and specifications, the requirements for PLL jitter are less stringent than systems with only an embedded clock.
Now that it is known which application stress which portion of the jitter spectrum, methods to cost-effectively mitigate them can be considered. For instance, the power-supply impact on jitter is not important for the first application (as long as there is no likely scenario of multi-GHz power-supply spikes).
However, such noise can have large impact on the second application, since a typical CDR bandwidth will only be in the tens of MHz range. In addition, a step response on the power supply will accumulate jitter until it gets corrected by PLL bandwidth. This will typically necessitate a regulator for such a PLL, causing additional area and power penalty. Even in the first application, a regulator may become necessary if there is requirement to cross from one clock domain to another, since long-term jitter starts to become important in that PLL.
PLLs are used everywhere, from within chip clocking to wireline data communication and RF systems. It is imperative to understand which particular application into which your PLL is going. Failure to do so will invariably lead to over-design or system failure.
1. Brig Assay, “Understand the jitter specification in oscilloscopes”, Planet Analog , April 1, 2011.(http://www.eetimes.com/design/analog-design/4214688/Understanding-the-jitter-specification-in-oscilloscopes)
About the author
Rohit Mittal is a passionate follower and practioner of analog/mixed-signal IC design. He has over 15 years of experience in this area with MSEE from Carnegie Mellon and BSEE from IIT Delhi, India. Rohit has 8 products (and about 100 derivative products) in high-volume production. He has worked on technologies ranging from 0.6μm BiCMOS to 32nm CMOS to SiGe and BCD. He has co-authored 7 IEEE journal papers. All of his designs have been sample-worthy on first silicon.