Understand analog/digital converter clock jitter–and why you should care

Clock jitter is a time variation in the clock time period. A beautiful ADC will yield poor signal-to-noise ratio (SNR), just because the clock edges are moving around. This article will look closely at clock jitter, and explore its causes and why it degrades ADC performance. It will also look into jitter solutions and how to examine potential clock sources for jitter problems.

What makes the clock jitter
In the circuit in Figure 1 , the comparator's output will go high if input B is greater than input A. It will fall when input B is less than input A. If the comparator and input signal sources are perfect, there is no jitter or noise. But the world is not perfect.

Look at input node A of the comparator (mystery zone). It is tied to a real-world input. It is bouncing around with noise, pulse reflections, and crosstalk. Due to the up-and-down movement of this node, it will move around the switching threshold of the comparator. This will make the jittery output seen the figure. In the imperfect world, the sinusoid will have noise of its own, further corrupting the output.

This mechanism is a primary cause of jitter within a design. In this example, I have shown a comparator. A similar architecture is used in logic gates, ADC clock inputs and clock sources. The nodes of any component suffer from the “bouncing around” of “dirty” switching nodes. Almost every component added between clock and ADC will add more jitter.

Figure 1: A simple comparator circuit illustrates the mechanism of jitter
(Click to enlarge image)

Types of jitter
There are two types of jitter:
Deterministic jitter is most often caused by the cross-coupling from other signals. Edges of switching signals, overshoot, and ringing are common causes of deterministic jitter. Also, 60-Hz power supply components will create large artifacts near the fundamental frequency.

Random jitter is primarily caused by thermal noise and electron flow, mostly as a result of electrons bouncing into atoms as they travel through conductors and components.

Phase noise
In Figure 2 , the period predominantly has a value of time A. However, every once in a while, the period's value is B and C. Occasionally, it is D and E. If you do a histogram plot of the occurrences of the period time values, it would likely look like the Gaussian bell curve at the bottom of the figure.

Figure 2: Variation of time period results in phase noise
(Click to enlarge image)

There is a variation of the time period between each clock cycle. The reciprocal of each time period can be defined as a frequency, with t = 1/f. This means the clock signal varies about a fundamental frequency. It also means that there is a collection of frequencies on the clock line, along with the fundamental clock frequency. On a basic level, this variation of period and frequency is phase noise.

This spread of frequencies will mix (convolve) with the analog frequency being digitized. They will add a spread to the fundamental and its harmonics. When the signal is analyzed by an FFT, this spread of frequencies will degrade the ADC's SNR, Figure 3 .

Figure 3: Spectral plot shows buried signal and spread in fundamental frequency which degrades SNR

In the ideal case, the spectral plot of the input signal would look like a flag pole in the grass. In the real world; however, there is some spread of signals around the base. This will degrade the SNR of the ADC, and it will mask the reception of lower-amplitude signals near the analog fundamental frequency. This base spread could be partially masked by window leakage from the FFT, but it is still present.

Time jitter
As the sample clock jitters left and right, it will acquire the input at different amplitudes. This sampling error manifests as noise (Vn ) in Figure 2. By taking the ratio of noise (Vn ) to signal (Va ) we can calculate SNR; after all, SNR is “signal-to-noise ratio.”

Jitter measurement and calculation
There is a relationship between analog input frequency, clock jitter and SNR. This relationship, which is plotted in Figure 4 , is defined as

SNR = 20 × log [1/(p × input frequency × Tj )]

where Tj = jitter time

Figure 4: Input frequency versus SNR and jitter
(Click to enlarge image)

There are instruments that can directly measure the jitter of a clock source. They include bit error rate (BER) test instruments and exotic oscilloscopes. Many jitter instruments will measure phase noise and then calculate time jitter.

A simpler way is to measure the SNR in an FFT and read it from Figure 4. National Semiconductor's WaveVision software, for example, will capture the data and plot an FFT, along with harmonic and SNR measurements. Many of National's competitors provide a similar ADC evaluation platform.

There are limitations to this method. The SNR measurement includes the jitter contributions of all the components of the system. These include clock source, clock drive circuits, and the ADC itself. Also, the FFT is affected by its number of points it uses, and the windowing function used with the FFT.

Why you care about jitter
Doppler applications: The Doppler mode of medical ultrasound or radar determines the velocity of blood flow, airplanes, or oncoming thunderstorms. The imager transmits a continuous wave (CW) signal into (or to) its target. It then measures the frequency shift of the reflected energy. The shifts in the received signal provide velocity information. This shift can be very small, especially in blood flow applications. The energy of Doppler shift can easily be lost in the jitter-related spreading around the ADC's fundamental frequency.

Communications applications: Communications systems often pick out many small signals, in the presence of stronger ones. These weak signals can also be lost in the jitter spread around a fundamental.

Cleaning up jitter
There are several things the designer can do to reduce and minimize jitter:

Layout: Good layout is all about keeping noisy currents from cross-coupling into the clock and signal lines. Poor layout is a big source of deterministic jitter. The ADC's output and external buffers will often switch all the bits at the same time. This switching will generate very large spikes of current on the ADC IC die and the external drive buffers. These spikes may cross-couple their way back to the clock and input lines, which will happen if the data lines are too close to the clock and analog-input lines. It will also happen if the digital return currents run under clock and analog input. This layout will add bounce to the “mystery zone” in Figure 1.

Superb signal sources: Today's converters are often better than the instruments used to provide signals. This is especially true of clock sources. In many ADC development labs, the “standard bearer” is the Agilent 8644B synthesizer. At the same time, vendors such as National Semiconductor are developing 14- and 16-bit converters which require rms clock jitter of less than 200 femtoseconds (fs). This is a very tough requirement for many signal sources.

Sometimes we get complaints about our evaluation boards. Customers in the field will say that they have measured the SNR of our product, and it is below the published specifications. When we investigate, we find they are using an old function generator with dubious noise and jitter specs. These inadequate sources degrade the converter's SNR.

For the external clock source, consider using an 8644B synthesizer (or equivalent) with a band-pass filter on its output. The filter will attenuate spurs from the clock source. It will also filter noise near the fundamental frequency.

Clock division: Jitter can also be reduced by multiplying the clock and dividing it back to the desired frequency. For example, the synthesizer will be set to 400 MHz and divided by 4 to produce a 100-MHz clock. The division can be done by using a divider such as an MC100EL33. This technique will take advantage of the high slew rates which are present at higher frequencies. The higher slew rate will decrease the time the sinusoid spends in the “mystery zone” (Figure 1), and will reduce the jitter.

While searching for low-jitter sources, I have discovered a number of great clock oscillators. Some of their data sheets specify jitter of more than 3 psec, but their behavior is much better. I begged samples from a number of vendors, and I also found an exotic clock source for $700 with “pristine specs.”

I used our ADC14C105 (14-bit, 105-Msps converter) evaluation board as a test platform. We have characterized its SNR at 72 dB with a 240-MHz analog input. This means its rms jitter is less than 180 fs. I set up one of our ADC14C105 boards and measured the SNR for each of the clock oscillators, with a 240-MHz analog-input signal.

The clear winners were the Pletronics 7745, the Vectron VCC1, and the Crystek 950, all powered by 5 V; the 3.3 V versions of these sources didn't perform as well. In quantity, these crystals cost from $1 to $30. The highly touted $700 crystal source wasn't as good as the “cheap” sources. If there is a moral to this story, it might be this: know your data sheets, and money isn't everything.

Good low-jitter oscillator candidates are designed to work with crystal overtones. As a general rule, when more things are added to the signal path, jitter will increase. This includes using a phase locked loop (PLL) to multiply the output frequency.

One question is: why do they specify such high jitter when I measured it to be so low? This might be in the way it is tested and specified. Jitter-measuring instruments often measure millions of points. This larger sample window will collect more spurious points. When I measure SNR with an FFT, I only take 64K points.

Clock jitter directly affects the SNR of an ADC. Careful board layout and clock selection will yield the highest levels of SNR. My claim of high SNR with inexpensive oscillators might seem silly. Therefore, I invite those designing with high-speed, high-resolution ADCs to follow my example. Collect a “box-o-clocks” and perform your own experiments!

1. Ramon Cerda, “Impact of Ultralow Phase Noise Oscillators on System Performance, ” RF Design , July 2006.
2. Vectron International, “Jitter in Clock Sources.”
3. Johnnie Hancock, “Jitter-Understanding It, Measuring It, Eliminating It,” High Frequency Electronics , April 2004.

About the author
Bill Odom is an Applications Engineer for the Data Conversion Division of National Semiconductor Corp. in Salem, New Hampshire. His focus at National is on the use of ADCs in medical ultrasound applications. He has spent the last 28 years in the design, application and test of ADCs, and has published several papers on getting the best from an ADC. Bill received his BSET degree from The New York Institute of Technology in Old Westbury NY.

0 comments on “Understand analog/digital converter clock jitter–and why you should care

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.