Understanding Factors Affecting Intel QuickPath Interconnect Signal Integrity (Part 1 of 2)

The Intel® QuickPath Interconnect operates at extremely high frequencies, so it is essential that circuit designers understand the many factors that affect differential signal integrity. This article introduces those factors and explains the basics of transmitting and receiving signals without significant distortion.

The objective of any electrical system design, from a signal integrity perspective, is to ensure that the signals transmitted by driving components are received without distortion significant enough to corrupt the data represented by those signals. This article introduces the primary factors to consider and control, for both parallel and serial differential bus designs:

  • Signal propagation or delay
  • Crosstalk
  • Reflective effects
  • Signal attenuation or loss
  • Jitter

Note that most of the factors discussed here apply both to Intel® QuickPath Interconnect (Intel QPI) and many other serial-differential (e.g. PCI Express™) and even single-ended interface designs.

This article is presented in two parts:

  • Part 1 covers signal propagation, delay, crosstalk, NEXT and FEXT, reflective effects, and impedance matching. To read it as a pdf document, click here.
  • Part 2 covers loss and jitter; it will be posted online on January 7, 2010.

This article is based on material found in the book Mastering High Performance Multiprocessor Signalling by Dave Coleman and Michael Mirmak. To go to the Intel Press web site to learn more about this book, click here.

About the Authors
Dave Coleman is a Staff Platform Application Engineer at Intel with 22 years of electrical engineering experience. At Intel, he specializes in enabling and integration of customer Intel® QuickPath Interconnect designs in Intel Server platforms. Dave is the coauthor of the PCI Express™ Electrical Interconnect Design book.

Michael Mirmak is a Technical Marketing Engineer at Intel Corporation. He has been involved with signal integrity modeling and simulation since 1996, developing platform guidelines and models for both processor and chipset products, in desktop, mobile and server applications. He has also served as chair of the IBIS Open Forum since 2003.

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