Configuring a phase locked loop (PLL) for a given frequency synthesis application can simultaneously be both a quick-and easy-process as well as a time-consuming, tedious, and iterative process. This dual nature in PLL system design arises from the number of loop parameters that need to be appropriately dialed in for a given application. As will be discussed in this article, there are two categories of loop parameters that must be considered: frequency synthesis parameters and performance parameters. The former sets up the loop to generate the correct frequency while the later dictates the quality of output frequency (with “quality” being a term relative to the given application).
The interplay between these two categories of parameters is where designers spend the bulk of their time. After determining a set of frequency synthesis parameters that meet the system needs, we then attempt to dial in the performance parameters. However, when we reach the end of optimizing the loop, there is always the doubt: did I choose the best possible frequency synthesis parameters? Perhaps there is a different set that will run cleaner and consume less power or have more margin? It is these design choices upon whicht this paper will attempt to shed some common-sense design principles.
An Overview of PLL Frequency Synthesis
At the most fundamental level, the goal of any frequency synthesizer is, based on a given reference frequency, to generate a desired output frequency. That is, solve:
(1)
where κ is the frequency scaling constant, sometimes referred to as the normalized frequency. Any frequency synthesizer circuit is simply a mechanism for approximating κ. A PLL frequency synthesizer approximates κ by inserting divide blocks between the reference oscillator and the output clock.
Then, using a feedback loop with a phase detector to maintain phase coherence between the two dividers, the desired frequency is generated. The block diagram for this is shown in Figure 1 . This is the general form of a charge pump integer divide phase locked loop (a very common topology used for frequency synthesis).
Three divide blocks are used to approximate the value of κ: the reference divider (Q), the feedback divider (P), and the output divider (N). It can be readily shown that κ is defined for this type of frequency synthesizer as: (2)
Combining Equations 1 and 2, the relationship between input and output frequency is:
(3)
It is these P, Q, and N divide values that we refer to as the “frequency synthesis parameters”. These values set up the gross functionality of the loop and must be chosen to set the desired output frequency. One common way of determining these values is to divide the output frequency by the reference frequency, and reduce the fraction:
(4)
The difficulty in solving Equation 4, for any arbitrary reference and output frequency, is that there are three degrees of freedom (limited only by the range of divide values P, Q, and N can take on). The most common technique for solving Equation 4 is a search algorithms. Such algorithms work by searching the solution space, looking for sets of P, Q, and N values that will result in the desired κ value. They are, in essence, triple nested loops that search all possible P, Q, and N values.
Common simplifications are to set N equal to one, Q equal to one, or both. These simplifications are based on system design needs. Analysis of all three of these simplifications is a subset of the general case shown in Figure 1 and represented by Equation 4.
If both Q and N are set equal to one, then the maximum resolution of the output frequency is limited to the reference frequency, making it possible to synthesize only integer multiples of the reference. In this case determining the value of P is reduced to a simple matter of arithmetic.
If just Q or N is set equal to one, then only a single configuration exists (with respect to a minimum Q/P or N/P ratio) for synthesizing the desired output. Determining this ratio is then a matter of fraction reduction.
The use of all three divide blocks introduces an added layer of generality to the hardware that enables the direct reuse of the PLL through programming for many different frequency synthesis applications. However, this generality also results in a significantly more complex problem in determining the values of P, Q, and N to use. Specifically, it results in multiple frequency synthesis parameter sets that are valid for a given reference and output frequency, all of which can have drastically different performance characteristics (band width, phase margin, jitter, phase noise, power consumption, etc).
An additional configuration that is commonly used in programmable systems on a chips (SoCs) is to have multiple output dividers. This allows for the synthesis of multiple outputs at different frequencies. Figure 2 illustrates this configuration. It is important to note that each output is an integer multiple of the VCO frequency. This topology emphasizes the importance of selecting the right VCO frequency so as to maximize the number of system clocks that can be generated off of the single PLL.
A Quick Walk Around the Loop
With the basic input-output relationship in hand, we next need to take a walk around the PLL and consider the steady-state operating condition. When the loop is in lock, the output of the Q divider and the P divider have matched phase and frequency and the output of the PFD is tri-stated, leaving the loop filter voltage unchanged and the VCO frequency steady. As the loop filter voltage changes (due to noise, charge pump leakage, and capacitor charge leakage), the VCO frequency will drift.
The PFD observes this drift by comparing the VCO output to the reference oscillator frequency (through the P and Q divides respectively) and causes the charge pump to either pump up or pump down the loop filter voltage. Once the correct loop filter voltage is reached again, the PFD output is tri-stated and the loop filter voltage is left unmodified.
During this normal mode of operation, the PFD frequency (the frequency at which the Phase-Frequency Detector runs) plays a central role. The PFD frequency is set by the reference oscillator frequency divided by the reference divider:
(5)
In the steady-state condition, the PLL loop dynamics force the VCO output frequency, divided by the P divider, to also be equal to the PFD frequency:
(6)
By re-arranging Equations 5 and 6, we can now make a key observation: the reference frequency and the VCO frequency must both have the PFD frequency as a common divisor :
(7)
Any valid choice of P and Q will result in a PFD frequency that is a common divisor of both the reference frequency and VCO frequency. This allows us to take a fundamentally different approach to determining the P and Q divide values than the fraction reduction method illustrated in equation (4). It is also worth noting that the PFD frequency will also play a central role in the PLL performance parameters, which we will discuss in more detail later. For now, let’s look at selecting the P and Q divide values based on the PFD frequency.
Determining P and Q Divide Values Based on the PFD Frequency
Since we know that the PFD frequency must be a common divisor of the reference frequency and VCO frequency, let’s choose it to be the greatest common divisor. By doing this we will minimize P and Q, and maximize the PFD frequency:
(8)
(9)
The range of valid VCO frequencies and N divide values is dictated by the following relationship:
(10a)
and all valid VCO frequencies are found by multiplying the list of N divide values by f_{out} :
(10b)
Thus, given a reference frequency and desired output frequency, we can use equations 8, 9, and 10 to determine all possible sets of frequency synthesis parameters (sets of P, Q and N). There is only one small problem with equations 8 and 9: the Greatest Common Divisor function is only defined on the set of integers. We usually want to synthesis real frequencies, not integer frequencies. This means that we need to make a few mathematical adjustments to equations 8 and 9 to make them useful in practical applications.
This is done by first recognizing that the reference frequency and output frequency are both real numbers, which implies that they can always be represented as ratios of integers:
(11)
By multiplying both fractions by their denominators we will transform them into integers (since the product of two integers is always an integer): :
(12)
(13)
We then can take the greatest common divisor of the result: :
(14)
This is almost the result we want. It is the GCD of two frequencies that are related to our original reference and VCO frequency. We can get back to the original values by dividing out the term we used to transform them: :
(15)
This result is equal of the greatest common divisor of our original reference frequency and VCO frequency. If we define a function called the greatest common divisor of rational numbers (GCDR) as: :
(16)
where
(17)
(note that LCM is the Least Common Multiple and den is the denominator part of f_{ref} and f_{vco} respectively), then we can solve for P and Q using the following equations:
(18)
(19)
By solving these equations for all VCO frequencies found in equation 10, the set of all divide values that will synthesize our desired output frequency from our given reference frequency is found.
This, however, is a lot of symbols; let’s now look at an illustrative example.
An Illustrative Example
For this example, we will synthesize a 50MHz output from a 14.3181818…MHz reference (a common video frequency). Assume the VCO has a frequency range of 100MHz to 400MHz.
First, all possible N divide values are determined using Equation 10:
Based on this list of N divide values, the corresponding VCO frequencies can be solved for and then the Q and P values can be solved for using Equation 18 and Equation 19. For N = 2, the following calculations are made:
All results for this example (N=2 through N=8) are shown in Table 1 . This is the complete set of frequency synthesis parameters that are possible given our reference frequency and desired output frequency.
Table 1. Summary of Example Results |
||||||
N |
Fref [MHz] |
fvco [MHz] |
Fout [MHz] |
fpfd [MHz] |
Q |
P |
2 |
14.318… |
100 |
50 |
0.227 |
63 |
440 |
3 |
14.318… |
150 |
50 |
0.682 |
21 |
220 |
4 |
14.318… |
200 |
50 |
0.227 |
63 |
880 |
5 |
14.318… |
250 |
50 |
0.227 |
63 |
1100 |
6 |
14.318… |
300 |
50 |
0.682 |
21 |
440 |
7 |
14.318… |
350 |
50 |
1.591 |
9 |
220 |
8 |
14.318… |
400 |
50 |
0.227 |
63 |
1760 |
Choosing an Optimal Configuration
Now that we have confidently found the set of all possible frequency synthesis parameters that meet our needs, we can turn our attention to selecting the performance parameters. Several common parameters that are optimized in various applications are: power consumption, startup time, settling time, jitter, and phase noise. Table 2 summarizes these parameters, the corresponding key loop parameters, the design equations needed for tradeoffs, and the how to optimize them. It is important to note the role that PFD frequency plays in each of these parameters.
Power
Power is dominated by the VCO frequency, charge pump current, and divide block settings. Most VCO architectures require larger tail currents to achieve higher frequencies. So as frequency increases, so does power consumption. Charge pump current is discharged once for each PFD period. When larger charge pump currents are required (for loop stability or fast startup / settling time) more power is consumed per PFD period. Clock dividers dissipate power at each clock edge. Larger clock divide values require more divide cells to transition, consuming more power.
Startup Time / Settling Time
The startup and settling time for a charge pump PLL is dominated by the loop natural frequency. This parameter can be thought of as the frequency slew rate of the PLL. It quantifies how fast the PLL can change the output frequency. It is proportional to the VCO gain and charge pump current, and inversely proportional to the feedback divide value and loop filter capacitance. Since the PLL output frequency is set by the VCO frequency, when we want to force a large step in the output frequency (either from zero at startup or from one setting to another) we need to force a large step in the VCO control voltage. This is accomplished by the charge pump dumping a large amount of charge onto the loop filter cap. The amount of frequency change per volt increase on the loop filter is set by the VCO gain. The rate at which the loop filter voltage is updated is set by the PFD frequency.
Jitter (Cycle-to-Cycle)
Cycle-to-Cycle jitter (the change in period length from one period to the next) can easily be dominated by the individual blocks of the PLL (VCO, dividers, reference oscillator), creating a situation where no loop parameter changes can improve performance. If you are working with a low noise PLL, then loop parameter settings can make a significant improvement.
Similar to startup time / settling time, the PFD frequency and VCO gain play a key role. Higher PFD frequencies mean that the PLL loop filter voltage is refreshed at a higher rate. This prevents the loop filter voltage from drifting. By using a large loop filter capacitance, the amount of voltage drift per PFD period is minimized. Because the VCO gain dictates how far the output frequency drifts per unit voltage drift on the loop filter, lower VCO gain makes the PLL less sensitive to loop filter voltage drift.
Phase Noise
Optimizing phase noise is highly application dependent, but a few general observations can be made. Phase noise contributed by the reference oscillator can be suppressed by setting the PLL to a lower closed loop bandwidth. Phase noise contributed by the VCO can be suppressed by setting the PLL to a higher closed loop bandwidth.
Phase noise divides down proportional to the output divide setting. If the output divider is a low noise divider, then running the VCO at a higher frequency and dividing the output frequency down will result in a phase noise improvement.
Optimizing the Illustrative Example
Finally let’s apply this general discussion on optimization to the list of PLL configurations that we found in the above example.
Power
If low power consumption is the primary design concern we want to minimize VCO frequency and divide values. Selecting N=3, Q=21, P=220 would be the best choice. This operates the VCO at one of the lower frequencies, lower P and Q values, and has a reasonable PFD frequency.
Startup / Settling Time
If startup / settling time is the primary concern, then from table 1 it is clear that the N=7, Q=9, P=220 is the most desirable. It has an f_{PFD} of more than two times any other configuration, resulting in a higher refresh rate on the loop filter voltage.
Jitter
If low jitter is the primary concern, then N=7, Q=9, P=220 is again the most desirable. It has an f_{PFD} of more than two times any other configuration, resulting in a higher refresh rate on the loop filter voltage and the lowest jitter of all the possible configurations.
Phase Noise
Optimizing phase noise is highly application dependent and depends on specific reference oscillator and VCO noise performance. The one design choice we can make based on our configuration list is to choose a high VCO frequency that is divided down. N=7, Q=9, P=220 is probably the best because its PFD frequency is so much higher than N=8, Q=63, P=1760. If the loop has high jitter, then the phase noise floor will rise significantly, swamping out any improvement the output divider is giving us.
Conclusion
Configuring a PLL for system applications can be an arduous task with lots of iteration. By first solving for all frequency synthesis parameters that meet our needs, we can then make well founded design choices that maximize flexibility and minimize cost.
About the author
Erik Mentze is a Senior Systems Engineer with Cypress Semiconductor Corp., developing system validation tests and test methodologies for their programmable system-on-chip product line. He holds a Bachelors of Science degree in both Mathematics and Electrical Engineering from the University of Idaho, as well as a Masters of Science degree in Electrical Engineering from the University of Idaho. Previously he has been a part of Cypress' programmable clock and wireless transceiver design groups, developing re-programmable, high-spectral purity, frequency-synthesis PLLs.
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