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USB PHY for 1.8-V devices offers SoC designers low power

Lisbon, Portugal—Analog/mixed-signal merchant IP supplier Chipidea introduced a USB PHY core for 1.8-V I/O devices that it says offers the industry's lowest power consumption for SoC designs in the 65-nm and 45-nm advanced technology nodes.

The Chipidea architecture provides a power consumption of approximately 70-mW. Fully compliant with the USB 2.0 specification, Chipidea's 1.8-V USB PHY guarantees D+ and D- protection to withstand transient short-circuit voltage without damage. The core also features analog programmability for fine-tuning.

The IP is available as a standalone PHY or matched with a USB controller.

“We are offering a new generation of USB IP cores using 1.8-V devices for designers that require the lowest power consumption,” said Celio Albuquerque, division director of Chipidea's Physical Solutions Division, in a statement. “This 1.8-V platform extends our portfolio to a new I/O device choice, while maintaining the advantages of our IP, including analog programmability, built-in self-test (BIST) and full USB2.0 compliance.”

Chipidea's certified USB cores are available at several of the industry's leading foundries and advanced process nodes. The IPs have been certified to provide design flexibility in the 0.18-micron, 0.13-micron, 90-nm and 65-nm process nodes.

For an on-demand Webinar entitled: Simplifying the Integration of High-Speed USB Into Your SoC, click here.

Chipidea, +351 21 033 63 00, www.chipidea.com

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