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User-Assisted, Automated Routing of Custom IC Designs, Part 1

Custom IC design is an integral part of competitiveness in the design of system-on-chip products. Even if the custom part of the chip is only 30 percent of the die, that 30 percent often accounts for 80 percent of the competitive differentiation. Coincidentally, it also often represents 80 percent of the engineering and verification effort.

While the demand for custom analog and mixed-signal ICs is increasing, so is the complexity of the analog circuitry and the degree of analog-digital integration. Yet, custom IC design remains a largely manual process. This was successful at larger technology nodes and in simpler designs, but the silicon world has become much too complicated and densely populated for it to work cost effectively today.

Manual routing is no longer intuitive and introduces too high of a schedule risk. Current verification solutions are able to catch gross errors, but miss those that are more subtle. Consequently, electrical parasitic errors are causing costly chip respins and layout iterations are causing missed R&D schedules. Custom IC designers desperately need automated assistance. Constraint-driven and interactive custom routing automation is the answer.

Living in a smaller, more complex world
In the analog world, transistors are more susceptible to environmental influences than digital. There are several challenges for AMS routing not found in digital ASIC routing, including hierarchical environments, a wide range of net width and space constraints, and no regular power mesh.

Figure 1

Densely packed hierarchical custom digital designs

Densely packed hierarchical custom digital designs

Analog designers need the ability to precisely control routing with large amounts of routed pre-wires and specialized routing for matching, symmetry, and shielding. They must consider and control many lithographic layout dependent effects and neighborhood influences on transistor behavior. Things like parasitic effects, matching, on-chip variation, spacing, and patterning have always been concerns, but at more aggressive technology nodes — 28 nm and below — it becomes a lot more difficult to control the die environment and all of its analog and analog-digital interactions.

Smaller transistors are more susceptible to process variations and effects. For this reason, designers must consider new geometric design rules when routing at more aggressive process technology nodes. Further, these geometric design rules influence electrical behavior such as common mode rejection. Routed patterns and shapes all have parasitics and influence each other electrically as well.

Yet it is very difficult, if not impossible, for the human mind to comprehend and keep track of the multitude of causes and effects, influences, and interactions that deep submicron technologies make possible. A fix for one problem may now result in several more problems, for seemingly random reasons. It’s a confoundingly complex relationship. This leaves designers wondering how they will ever converge on the specification. What they need is more automation to bring order to this apparent chaos.

Making sense of a complex world
A constraint-based custom router using sophisticated algorithms can help untangle these complex relationships. The custom router must be interactive, so that the analog engineer can guide the automation process using his expertise about analog mixed-signal design and knowledge of specific design goals. This type of guided automation will make the designer more productive in this challenging environment. There are several ways designers can use constraints to do this.

One is to make the topology correct-by-construction by using constraints to create better matching and parasitics. A constraint mechanism, built into a custom router, allows designers to put different constraints on nets of interest and ensure that the router adheres to those constraints and implements topologies that meet them. This is especially important (and difficult) in analog designs because as much as 80 percent of the nets may have constraints on them. The amount of constraints is so high because parasitic effects must be controlled by the topology; in terms of how it gets put down, the metal layers it uses, the width of the wire, and the space between a wire and other wires may influence it.

All of these things are traditionally done by hand, but the denser the chip becomes and the more interactions there are, the harder it is to do. When it can be done, it takes a long time and, because of schedule pressures, the designer may have only one shot to get it done right. On the other hand, a custom router can do millions of iterations to find the best topology per the constraints within a much shorter period of time. A layout that took a month can now be routed in a day, enabling tapeouts to be on-time and allowing designers to further optimize routing because they now have time to do more iterations.

In Part 2, we will continue looking at the advantages of a constraint-based router compared to manual routing in complex, mixed signal ICs.

9 comments on “User-Assisted, Automated Routing of Custom IC Designs, Part 1

  1. DEREK.KOONCE
    June 11, 2013

    If one was to pull down a chip design software package, would the package provide basic input circuit layouts for I/O pads? Will the software have a basic quick-layout of the memory?

    I never have done chip layouts, but am curious as to the ability of one to minimize errors when starting out or doing a personal IC layout.

  2. Davidled
    June 11, 2013

    I guess that automatic routing functionality might be depending on what type tool might be used. Automatic routing could be completed, but IC designer might have to look at the optimization of routine. I do not think that all engineering tool provides 100% auto routing, based on internal algorithm. Combination of automatic and manual routing might be a best choice.

  3. Netcrawl
    June 12, 2013

    @Daej yes it could be a good choice some design have different requirement. I think in dealing with those design it would much better if we used or combined those two things. 

  4. Brad Albing
    June 12, 2013

    @Derek – looks like it's time you looked into IC design – especially if the comments following Scott Elder's blog by KCP prove valid (re the “The Innovator's Dilemma”):

    http://www.planetanalog.com/author.asp?section_id=526&doc_id=560151&

  5. Mitchell Heins
    June 12, 2013

    Derek sorry for the late response.  I travel a lot.

    In general the software packages you buy from the likes of Mentor Graphics (who I work for), Cadence and Synopsys do not provide circuit layouts for your use.  They may or may not have tutorials using some basic layout to show how the tool is used but real layout is left to the professional IC designers.  There are a variety of reasons for this including legal liabilties, a plethora of silicon processes to choose from along with their associated design rules and probably most importantly the fact that some of these companies actually sell those types of layouts as intellectual property (IP).

    IC layout is an expensive proposition these days.  Getting wafter capacity, reticle costs, packaging etc. requires a complicated and expensive supply chain.  If you are serious about this I would suggest start with design first and find yourself a good competent design house to do the implementation.  Then if you still think you can make money after that experience you'll have something to go by.

     

  6. RedDerek
    June 12, 2013

    Thanks for the info. I can now see the legal issues. But having some basic examples would help out a person getting into this on the side. Now to find some good books.

  7. Scott Elder
    June 12, 2013

    @RedDerek

    You can get access to pad layouts, digital cell and component layouts, etc. from the foundries.  Then you just need one of the free PC tools to look at the layouts.

    The problem will be the time involved to setup.  Get the layout tool up and running.  Stream in the cells from the foundry.  That's all free if you don't count time.

     

     

  8. Scott Elder
    June 12, 2013

    Here's a little more detail on how to get started.

    http://www.planetanalog.com/author.asp?section_id=526&doc_id=559519

  9. Brad Albing
    June 24, 2013

    An excellent article. It should be promoted more often. Thanks.

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