Custom IC design is an integral part of competitiveness in the design of system-on-chip products. Even if the custom part of the chip is only 30 percent of the die, that 30 percent often accounts for 80 percent of the competitive differentiation. Coincidentally, it also often represents 80 percent of the engineering and verification effort.
While the demand for custom analog and mixed-signal ICs is increasing, so is the complexity of the analog circuitry and the degree of analog-digital integration. Yet, custom IC design remains a largely manual process. This was successful at larger technology nodes and in simpler designs, but the silicon world has become much too complicated and densely populated for it to work cost effectively today.
Manual routing is no longer intuitive and introduces too high of a schedule risk. Current verification solutions are able to catch gross errors, but miss those that are more subtle. Consequently, electrical parasitic errors are causing costly chip respins and layout iterations are causing missed R&D schedules. Custom IC designers desperately need automated assistance. Constraint-driven and interactive custom routing automation is the answer.
Living in a smaller, more complex world
In the analog world, transistors are more susceptible to environmental influences than digital. There are several challenges for AMS routing not found in digital ASIC routing, including hierarchical environments, a wide range of net width and space constraints, and no regular power mesh.
Analog designers need the ability to precisely control routing with large amounts of routed pre-wires and specialized routing for matching, symmetry, and shielding. They must consider and control many lithographic layout dependent effects and neighborhood influences on transistor behavior. Things like parasitic effects, matching, on-chip variation, spacing, and patterning have always been concerns, but at more aggressive technology nodes — 28 nm and below — it becomes a lot more difficult to control the die environment and all of its analog and analog-digital interactions.
Smaller transistors are more susceptible to process variations and effects. For this reason, designers must consider new geometric design rules when routing at more aggressive process technology nodes. Further, these geometric design rules influence electrical behavior such as common mode rejection. Routed patterns and shapes all have parasitics and influence each other electrically as well.
Yet it is very difficult, if not impossible, for the human mind to comprehend and keep track of the multitude of causes and effects, influences, and interactions that deep submicron technologies make possible. A fix for one problem may now result in several more problems, for seemingly random reasons. It’s a confoundingly complex relationship. This leaves designers wondering how they will ever converge on the specification. What they need is more automation to bring order to this apparent chaos.
Making sense of a complex world
A constraint-based custom router using sophisticated algorithms can help untangle these complex relationships. The custom router must be interactive, so that the analog engineer can guide the automation process using his expertise about analog mixed-signal design and knowledge of specific design goals. This type of guided automation will make the designer more productive in this challenging environment. There are several ways designers can use constraints to do this.
One is to make the topology correct-by-construction by using constraints to create better matching and parasitics. A constraint mechanism, built into a custom router, allows designers to put different constraints on nets of interest and ensure that the router adheres to those constraints and implements topologies that meet them. This is especially important (and difficult) in analog designs because as much as 80 percent of the nets may have constraints on them. The amount of constraints is so high because parasitic effects must be controlled by the topology; in terms of how it gets put down, the metal layers it uses, the width of the wire, and the space between a wire and other wires may influence it.
All of these things are traditionally done by hand, but the denser the chip becomes and the more interactions there are, the harder it is to do. When it can be done, it takes a long time and, because of schedule pressures, the designer may have only one shot to get it done right. On the other hand, a custom router can do millions of iterations to find the best topology per the constraints within a much shorter period of time. A layout that took a month can now be routed in a day, enabling tapeouts to be on-time and allowing designers to further optimize routing because they now have time to do more iterations.
In Part 2, we will continue looking at the advantages of a constraint-based router compared to manual routing in complex, mixed signal ICs.