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User-Assisted, Automated Routing of Custom IC Designs, Part 2

In Part 1, we looked at the problems of manual routing in complex, mixed signal ICs. We then looked at some of the advantages of a constraint-based router. Continuing the discussion of the constraint-based router, we'll look at additional advantages.

Constraints also make it easy to quickly handle specification changes , because the analog designer only has to reset the constraints and re-route the topology. Users of automated, interactive custom routers have reported a 10x productivity increase because of this. If change orders come in, even late in the design cycle, the schedule impact can be mitigated because it only takes a day to redo the routing.

The speed of assisted custom router automation enables designers to explore what if scenarios because it gives them the time to explore the effects of various constraint settings. For example, when moving to new technology nodes, the router can be run early in the design flow to evaluate different floorplans. This allows the design team to see the impact of different spacing, patterning, and wire widths on the amount of real estate required early in the cycle. Not only does this make for more efficient designs, it also eliminates time-consuming area adjustments late in the cycle.

Giving a custom router greater control over the topology is another way to improve productivity. There are several ways this can be done.

Constraints can direct the custom router to make routing choices that meet other criteria besides satisfying the design rules. For example, a normal auto router will connect a piece of metal with one or two vias and be done. While this is legal from a design rules perspective, from a designer’s viewpoint it is a terrible connection because it is highly resistive. Instead, a designer would run many vias in parallel to lower the resistance. The ability to constrain the custom router to make sure the topology reflects how a human would do it is very important.

Constraints can be fed into the router so that it mimics the way designers balance the current flow. Because its primary directive is to save real estate, a digital router will choose the shortest distance between two points, as long as it adheres to the design rules. Yet, a designer often will route a more roundabout connection in order to balance the current flow coming off of a particular structure. This is critical in analog routing because current flow is often used to control analog circuit behavior.

Constraints can be used to achieve self-symmetry , which is where the loads in a single net are balanced for good electrical characteristics. This can also be extended to two nets by making one a mirror image of the other in order to match the parasitics of each one. The two nets are symmetrically routed so that every via and metal trace in each net is identical, meaning the current flowing through each net is identical.

Designers can also use constraints for differential pair routing. A differential pair, in this context, exists when two nets are running side by side. If there is any noise on these lines, the noise on both lines will be the same because they’re right next to each other. The designer can run shields on either side of the two nets and tie them into power rails. This allows designers to isolate the common noise on these nets so they can filter common mode noise out of the electrical signals.

These topology constraints are not available in the typical digital routers used for SoCs. Yet designers need them for custom IC design. The Pyxis Custom Router from Mentor Graphics enables this kind of constraint-driven routing for both custom analog and custom digital designs. Its integrated, advanced, custom routing functionalities include a global router for congestion mitigation and a detailed signal router with a sophisticated net-by-net and layer-by-layer constraint mechanism that enables it to mimic layouts done by human designers in a fraction of the time while adhering to all of the complex design rules.

Next up: Placement and floorplanning
Today, custom IC design is largely a manual process; this is especially true of the critical routing step. This leads to long routing schedules and errors that go uncaught. Sophisticated, constraint-based routing automation resolves this expensive crisis, reducing errors and respins, improving design schedules, lowering the cost of R&D, and improving design quality.

The next solution EDA companies need to deliver are constraints that enable assisted-automated placement for analog and mixed signal custom designs that can work hand in hand with interactive custom routing. This should be followed by constraint-driven hierarchical floorplanning tools that can deal with the complex requirements for power, IR drop, and thermal design.

Once this triad is in place, analog and mixed signal designers working on modern SoCs will have solutions that help them more efficiently and optimally place, route, and architect their designs with all the precision of a fully manual process, but much faster.

10 comments on “User-Assisted, Automated Routing of Custom IC Designs, Part 2

  1. DEREK.KOONCE
    June 12, 2013

    Great set of articles. I look forward to the next installment. I am still waiting to see if canned layouts will be provided by the fab houses to cover the basics such as I/O protection circuitry, canned layout for a 8x8M RAM (I show my age here), and so forth.

  2. bjcoppa
    June 12, 2013

    Amid the growth in mobile devices taking over the computing world, it offers an array of new opportunities for EDA companies. As foundries such as TSMC obtain more business and outsourcing continues for a wider selection of smartphones, tablets and fablets (phone-tablets on the way), there is an increased need for EDA for IC firms without fabs. It is more critical to predict future winning designs over having large fab capacity. That is why ARM is winning the roadmaps of mobile device chips.

  3. Brad Albing
    June 14, 2013

    @analoging >>fablets (phone-tablets) … It's a good name, but the device seems impractical – holding a tablet up to your ear seems like a pretty awkward thing to do. Unless there is a separate headset piece – but then that's one more thing you'd have to carry around – or accidentally leave behind. Inconvenient any way you slice it.

  4. bjcoppa
    June 14, 2013

    Your points are well taken and that may be why the idea is only discussed at conferences and is not commercially available as of yet. However, high-end smartphones are getting larger mainly for a bigger screen as in Samsung Galaxy S4 while  tablets are shrinking as in the mini iPad. There may be a sweet spot in between for a fablet!

  5. Via Monger
    June 15, 2013

    @Brad-Albing >>fablets is not only a good name but an incredibly practicle device.

    The problem is we are getting old [I did say we]. We (us old folks) still think a phone is for talking. The generation(s) really consuming these fablet-sized devices rarely use the phone function of their phone. 

    As Nicholas Negroponte forecast in “Being Digital” (1995), what was broadcast will become narrowcast. A fablet is a narrowcast mobile media consumption and generation device – watch videos, generate videos, games, apps, social and texting. The talking on the phone functionality seems like an aftertought to many users of these products. 

    The good news for us analog and mixed signal folk is that these products require a tremendous amount of sensor processing and user interface circuits that are profoundly analog. Pretty exciting to see new fabs in larger geometries being planned simply to support the analog needs of these products.

     

  6. Davidled
    June 15, 2013

    Recently, Intel announced that Z2580 application processor outperformed other company processor through benchmarks comparing Lenovo K900 smartphone that is based on Z2580 with Samsung smart phone powered by ARM-based application processor such as Qualcomm and Nvidia. Benchmark is conducted in terms of chip performance and current consumption. Intel has a better position in the mobile market.

    Link is: http://www.eetimes.com/design/communications-design/4416220/Intel-processor-outperforms-Nvidia–Qualcomm–Samsung-ICs?cid=Newsletter+-+EETimes+Daily

     

  7. Herby6262
    June 15, 2013

    Router hardware (especially high end h/w) and it's design is not my strong-suit or background, but just as a thought, would something like Texas Instrument's highest end DSP running say even a home-brew written scheduler for threading priority be able to even come close to handling something like that?  Or is this generally done using small form-factor SBCs?  I've seen entire aircraft display systems running from a single DSP board.  Though if there are heavy amounts of analog inputs, maybe that's just naturally not such a good choice.

  8. Brad Albing
    June 16, 2013

    @Via Man – point taken – no one talks anymore – just types or shoots pics.

  9. Brad Albing
    June 24, 2013

    @DaeJ – thanks for the link.

  10. Brad Albing
    June 24, 2013

    @Herby – nothing but the sound of crickets greeting you for an answer. Looks like we'll need to find a different forum to get an answer.

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