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Using Deep N Wells in Analog Design

On a conventional CMOS process (see figure 1), NMOS devices are formed in a P well or substrate connected to ground (or the most negative supply in the circuit). PMOS devices are formed in an N well connected to the most positive supply.

Figure 1

A typical CMOS inverter cross section. Substrate noise currents are shown as red lines.

A typical CMOS inverter cross section. Substrate noise currents are shown as red lines.

Substrate noise caused by minority carrier injection into the substrate and well can be collected by the use of well taps and/or guard rings. An additional problem exists in that capacitive coupling of noise from the well to the substrate means more noise reaches the supply. In digital circuitry this is usually not a problem owing to the relatively high noise immunity of logic gates. However in analog design, for example a 12 bit ADC, noise can be a serious problem. A variety of techniques can be used to minimise this noise, for example by keeping analog devices surrounded by guard rings, or using a separate supply for the substrate/well taps. However guard rings alone cannot prevent noise coupling deep in the substrate, only surface currents.

Another problem is that it is not possible to isolate NMOS devices. So relatively noisy digital logic cannot be isolated completely from more sensitive analog areas.

A solution is to isolate the NMOS devices by using an extra well – a ‘deep N well’. So in figure 2 the NMOS device is fabricated in a P well or substrate completely surrounded by an N type diffusion.

Figure 2

A deep N well CMOS inverter cross section. Substrate noise currents are shown as red lines.

A deep N well CMOS inverter cross section. Substrate noise currents are shown as red lines.

In this case, the deep N well is formed by a high energy ion implantation to give peak impurity concentration deep enough to un-affect the NMOS device performance1 . Connection to the deep N well is formed by a N well ring that is connected to VDD. The deep N well has the effect of decreasing the noise coupling through it to the substrate and giving the advantage of fully isolated NMOS devices – which can in theory be at a different potential from ground.

The implications on layout are of course larger area for nmos devices due to the extra N well rings used to connect to the deep N well. However the noise performance improvements justify this for sensitive analog design.

In summary, the use of deep N well devices can significantly reduce noise coupling between sensitive analog areas and more noisy digital regions in mixed-signal designs.

For more information on challenges in modern analog design download the latest white paper.

Reference

1 ESSDERC 2012

2 comments on “Using Deep N Wells in Analog Design

  1. dick_freebird
    May 7, 2015

    Curious about your take on the relative merits of a deep Nwell

    and a thick film SOI (partially depleted) for analog performance,

    noise, layout density and cost.

     

    My observation is that density may be a wash (DNW oversize

    of Pwell often being quite large, but dtrench also needing a lot

    of room to minimize strain effects), SOI having an absolute lack

    of substrate leakage and an ability to make each device body

    ohmically tied & independent, but DNW having only two added

    implants vs the greater challenges of high aspect ratio trenching

    (and potentially some poly-routing contraints, like no poly over

    trench).

     

    Have you an opinion, or direct comparo data, on the performance

    when it comes particularly to noise limited analog performance,

    between these two approaches?

  2. Keith Sabine
    May 8, 2015

    There has been some research into noise performance of SOI compared to deep N well process technology (I can't publish the link, this site won't allow URL posting) but if you google for “Evaluation of package and technology effects on substrate-crosstalk isolation in CMOS RFIC” you should find it.

    The problem is that with SOI, the coupling capacitance from the devices is relatively high, as shown in the paper, and the noise performance is worse than deep N well technology. And then you have the cost overhead of SOI wafers over conventional silicon.

    Silicon on sapphire would get round the substrate coupling, but not the cost issue, and has long been used for rad-hard environments, where cost is not a real problem.

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